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No commits in common. "711b68608dff2e9474f9b2ce14a8066119d141a3" and "1d7c47e630da60870f8d862548c3d628b7c3c6e1" have entirely different histories.
711b68608d
...
1d7c47e630
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@ -92,15 +92,15 @@ case 0x7C: JMP( addr_ind_ind_X()); return 6; // abs_addr_X() ); return 6;
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case 0xFA: PLX(); return 4; // PLX
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// STZ - STore Zero
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case 0x64: STZ_zp( addr_zp() ); return 3; // STZ zpg
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case 0x74: STZ_zp( addr_zp_X() ); return 4; // STZ zpg,X
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case 0x64: STZ( addr_zp() ); return 3; // STZ zpg
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case 0x74: STZ( addr_zp_X() ); return 4; // STZ zpg,X
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case 0x9C: STZ( addr_abs() ); return 4; // STZ abs
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case 0x9E: STZ( addr_abs_X() ); return 5; // STZ abs,X
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// TRB - Test and Reset Bits
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case 0x04: TSB_zp( addr_zp() ); return 5; // TSB zpg
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case 0x04: TSB( addr_zp() ); return 5; // TSB zpg
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case 0x0C: TSB( addr_abs() ); return 6; // TSB abs
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case 0x14: TRB_zp( addr_zp() ); return 5; // TRB zpg
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case 0x14: TRB( addr_zp() ); return 5; // TRB zpg
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case 0x1C: TRB( addr_abs() ); return 6; // TRB abs
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@ -1,5 +1,4 @@
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//
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//
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// 6502_std.h
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// A2Mac
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//
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@ -36,7 +35,7 @@
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case 0x01: ORA( src_X_ind() ); return 6; // ORA X,ind
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case 0x05: ORA( src_zp() ); return 3; // ORA zpg
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case 0x06: ASL_zp( addr_zp() ); return 5; // ASL zpg
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case 0x06: ASL( addr_zp() ); return 5; // ASL zpg
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case 0x08: PHP(); return 3; // PHP
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case 0x09: ORA( imm() ); return 2; // ORA imm
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@ -49,7 +48,7 @@
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case 0x11: ORA( src_ind_Y() ); return 5; // ORA ind,Y
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case 0x15: ORA( src_zp_X() ); return 4; // ORA zpg,X
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case 0x16: ASL_zp( addr_zp_X() ); return 6; // ASL zpg,X
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case 0x16: ASL( addr_zp_X() ); return 6; // ASL zpg,X
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case 0x18: CLC(); return 2; // CLC
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case 0x19: ORA( src_abs_Y() ); return 4+1; // ORA abs,Y
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@ -62,7 +61,7 @@
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case 0x24: BIT( src_zp() ); return 3; // BIT zpg
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case 0x25: AND( src_zp() ); return 3; // AND zpg
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case 0x26: ROL_zp( addr_zp() ); return 5; // ROL zpg
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case 0x26: ROL( addr_zp() ); return 5; // ROL zpg
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case 0x28: PLP(); return 4; // PLP
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case 0x29: AND( imm() ); return 2; // AND imm
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@ -76,7 +75,7 @@
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case 0x31: AND( src_ind_Y() ); return 5; // AND ind,Y
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case 0x35: AND( src_zp_X() ); return 4; // AND zpg,X
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case 0x36: ROL_zp( addr_zp_X() ); return 6; // ROL zpg,X
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case 0x36: ROL( addr_zp_X() ); return 6; // ROL zpg,X
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case 0x38: SEC(); return 2; // SEC
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case 0x39: AND( src_abs_Y() ); return 4+1; // AND abs,Y
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@ -88,7 +87,7 @@
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case 0x41: EOR( src_X_ind() ); return 6; // EOR X,ind
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case 0x45: EOR( src_zp() ); return 3; // EOR zpg
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case 0x46: LSR_zp( addr_zp() ); return 5; // LSR zpg
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case 0x46: LSR( addr_zp() ); return 5; // LSR zpg
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case 0x48: PHA(); return 3; // PHA
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case 0x49: EOR( imm() ); return 2; // EOR imm
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@ -102,7 +101,7 @@
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case 0x51: EOR( src_ind_Y() ); return 5; // EOR ind,Y
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case 0x55: EOR( src_zp_X() ); return 4; // AND zpg,X
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case 0x56: LSR_zp( addr_zp_X() ); return 6; // LSR zpg,X
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case 0x56: LSR( addr_zp_X() ); return 6; // LSR zpg,X
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case 0x58: CLI(); return 2; // CLI
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case 0x59: EOR( src_abs_Y() ); return 4+1; // EOR abs,Y
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@ -114,7 +113,7 @@
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case 0x61: ADC( src_X_ind() ); return 6; // ADC X,ind
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case 0x65: ADC( src_zp() ); return 3; // ADC zpg
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case 0x66: ROR_zp( addr_zp() ); return 5; // ROR zpg
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case 0x66: ROR( addr_zp() ); return 5; // ROR zpg
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case 0x68: PLA(); return 4; // PLA
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case 0x69: ADC( imm() ); return 2; // ADC imm
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@ -128,7 +127,7 @@
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case 0x71: ADC( src_ind_Y() ); return 5; // ADC ind,Y
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case 0x75: ADC( src_zp_X() ); return 4; // ADC zpg,X
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case 0x76: ROR_zp( addr_zp_X() ); return 6; // ROR zpg,X
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case 0x76: ROR( addr_zp_X() ); return 6; // ROR zpg,X
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case 0x78: SEI(); return 2; // SEI
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case 0x79: ADC( src_abs_Y() ); return 4+1; // ADC abs,Y
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@ -138,9 +137,9 @@
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case 0x81: STA( addr_ind_X() ) ; return 6; // STA X,ind
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case 0x84: STY_zp( addr_zp() ); return 3; // STY zpg
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case 0x85: STA_zp( addr_zp() ); return 3; // STA zpg
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case 0x86: STX_zp( addr_zp() ); return 3; // STX zpg
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case 0x84: STY( addr_zp() ); return 3; // STY zpg
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case 0x85: STA( addr_zp() ); return 3; // STA zpg
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case 0x86: STX( addr_zp() ); return 3; // STX zpg
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case 0x88: DEY(); return 2; // DEY
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@ -153,9 +152,9 @@
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case 0x90: BCC( rel_addr() ); return 2; // BCC rel
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case 0x91: STA( addr_ind_Y() ); return 6; // STA ind,Y
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case 0x94: STY_zp( addr_zp_X() ); return 4; // STY zpg,X
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case 0x95: STA_zp( addr_zp_X() ); return 4; // STA zpg,X
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case 0x96: STX_zp( addr_zp_Y() ); return 4; // STX zpg,Y
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case 0x94: STY( addr_zp_X() ); return 4; // STY zpg,X
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case 0x95: STA( addr_zp_X() ); return 4; // STA zpg,X
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case 0x96: STX( addr_zp_Y() ); return 4; // STX zpg,Y
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case 0x98: TYA(); return 2; // TYA
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case 0x99: STA( addr_abs_Y() ); return 5; // STA abs,Y
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@ -199,7 +198,7 @@
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case 0xC4: CPY( src_zp() ); return 3; // CPY zpg
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case 0xC5: CMP( src_zp() ); return 3; // CMP zpg
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case 0xC6: DEC_zp( addr_zp() ); return 5; // DEC zpg
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case 0xC6: DEC( addr_zp() ); return 5; // DEC zpg
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case 0xC8: INY(); return 2; // INY
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case 0xC9: CMP( imm() ); return 2; // CMP imm
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@ -213,7 +212,7 @@
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case 0xD1: CMP( src_ind_Y() ); return 5; // CMP ind,Y
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case 0xD5: CMP( src_zp_X() ); return 4; // CMP zpg,X
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case 0xD6: DEC_zp( addr_zp_X() ); return 6; // DEC zpg,X
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case 0xD6: DEC( addr_zp_X() ); return 6; // DEC zpg,X
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case 0xD8: CLD(); return 2; // CLD
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case 0xD9: CMP( src_abs_Y() ); return 4; // CMP abs,Y
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@ -226,7 +225,7 @@
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case 0xE4: CPX( src_zp() ); return 3; // CPX zpg
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case 0xE5: SBC( src_zp() ); return 3; // SBC zpg
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case 0xE6: INC_zp( addr_zp() ); return 5; // INC zpg
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case 0xE6: INC( addr_zp() ); return 5; // INC zpg
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case 0xE8: INX(); return 2; // INX
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case 0xE9: SBC( imm() ); return 2; // SBC imm
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@ -240,7 +239,7 @@
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case 0xF1: SBC( src_ind_Y() ); return 5; // SBC ind,Y
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case 0xF5: SBC( src_zp_X() ); return 4; // SBC zpg,X
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case 0xF6: INC_zp( addr_zp_X() ); return 6; // INC zpg,X
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case 0xF6: INC( addr_zp_X() ); return 6; // INC zpg,X
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case 0xF8: SED(); return 2; // SED
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case 0xF9: SBC( src_abs_Y() ); return 4+1; // SBC abs,Y
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@ -39,21 +39,10 @@
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absolute,X INC oper,X FE 3 7
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**/
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#ifndef DISASSEMBLER
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INSTR void _INC_zp( uint16_t addr ) {
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set_flags_NZ( ++(WRZEROPG[addr]) );
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}
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INSTR void _INC( uint16_t addr ) {
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set_flags_NZ( ++(WRLOMEM[addr]) );
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}
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#endif
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INSTR void INC_zp( uint16_t addr ) {
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disPrintf(disassembly.inst, "INC");
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#ifndef DISASSEMBLER
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_INC_zp(addr);
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#endif
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}
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#endif
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INSTR void INC( uint16_t addr ) {
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disPrintf(disassembly.inst, "INC");
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@ -136,20 +125,10 @@ INSTR void INA() {
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absolute,X DEC oper,X DE 3 7
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**/
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#ifndef DISASSEMBLER
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INSTR void _DEC_zp( uint16_t addr ) {
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set_flags_NZ( --(WRZEROPG[addr]) );
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}
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INSTR void _DEC( uint16_t addr ) {
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set_flags_NZ( --(WRLOMEM[addr]) );
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}
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#endif
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INSTR void DEC_zp( uint16_t addr ) {
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disPrintf(disassembly.inst, "DEC");
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#ifndef DISASSEMBLER
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_DEC_zp(addr);
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#endif
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}
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INSTR void DEC( uint16_t addr ) {
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disPrintf(disassembly.inst, "DEC");
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@ -141,13 +141,6 @@ INSTR void STA( uint16_t addr ) {
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STR(addr, m6502.A);
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#endif
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}
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INSTR void STA_zp( uint8_t addr ) {
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dbgPrintf("STA ");
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disPrintf(disassembly.inst, "STA");
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#ifndef DISASSEMBLER
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STR_zp(addr, m6502.A);
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#endif
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}
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/**
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STX Store Index X in Memory
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@ -168,13 +161,6 @@ INSTR void STX( uint16_t addr ) {
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STR(addr, m6502.X);
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#endif
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}
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INSTR void STX_zp( uint8_t addr ) {
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dbgPrintf("STX ");
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disPrintf(disassembly.inst, "STX");
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#ifndef DISASSEMBLER
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STR_zp(addr, m6502.X);
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#endif
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}
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/**
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STY Sore Index Y in Memory
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@ -195,13 +181,6 @@ INSTR void STY( uint16_t addr ) {
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STR(addr, m6502.Y);
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#endif
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}
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INSTR void STY_zp( uint18_t addr ) {
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dbgPrintf("STY ");
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disPrintf(disassembly.inst, "STY");
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#ifndef DISASSEMBLER
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STR_zp(addr, m6502.Y);
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#endif
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}
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/**
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STZ Store Zero (0) in Memory
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@ -223,13 +202,6 @@ INSTR void STZ( uint16_t addr ) {
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STR(addr, 0);
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#endif
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}
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INSTR void STZ_zp( uint8_t addr ) {
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dbgPrintf("STZ ");
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disPrintf(disassembly.inst, "STZ");
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#ifndef DISASSEMBLER
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STR_zp(addr, 0);
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#endif
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}
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#endif // __6502_INSTR_LOAD_STORE_H__
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@ -86,15 +86,6 @@ INSTR void LSR( uint16_t addr ) {
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set_flags_NZ( WRLOMEM[addr] >>= 1 );
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#endif
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}
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INSTR void LSR_zp( uint16_t addr ) {
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dbgPrintf("LSR ");
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disPrintf(disassembly.inst, "LSR");
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#ifndef DISASSEMBLER
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m6502.C = WRZEROPG[addr] & 1;
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set_flags_NZ( WRZEROPG[addr] >>= 1 );
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#endif
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}
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INSTR void LSRA() {
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dbgPrintf("LSR ");
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disPrintf(disassembly.inst, "LSR");
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@ -126,12 +117,6 @@ INSTR void _ROL( uint16_t addr ) {
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WRLOMEM[addr] <<= 1;
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set_flags_NZ( WRLOMEM[addr] |= C );
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}
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INSTR void _ROL_zp( uint16_t addr ) {
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uint8_t C = m6502.C != 0;
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m6502.C = WRZEROPG[addr] & 0x80;
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WRZEROPG[addr] <<= 1;
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set_flags_NZ( WRZEROPG[addr] |= C );
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}
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#endif
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INSTR void ROL( uint16_t addr ) {
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dbgPrintf("ROL ");
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@ -141,14 +126,6 @@ INSTR void ROL( uint16_t addr ) {
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_ROL(addr);
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#endif
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}
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INSTR void ROL_zp( uint16_t addr ) {
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dbgPrintf("ROL ");
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disPrintf(disassembly.inst, "ROL");
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#ifndef DISASSEMBLER
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_ROL_zp(addr);
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#endif
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}
|
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INSTR void ROLA() {
|
||||
dbgPrintf("ROL ");
|
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disPrintf(disassembly.inst, "ROL");
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@ -182,12 +159,6 @@ INSTR void _ROR( uint16_t addr ) {
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WRLOMEM[addr] >>= 1;
|
||||
set_flags_NZ( WRLOMEM[addr] |= C << 7 );
|
||||
}
|
||||
INSTR void _ROR_zp( uint16_t addr ) {
|
||||
uint8_t C = m6502.C != 0;
|
||||
m6502.C = WRZEROPG[addr] & 1;
|
||||
WRZEROPG[addr] >>= 1;
|
||||
set_flags_NZ( WRZEROPG[addr] |= C << 7 );
|
||||
}
|
||||
#endif
|
||||
INSTR void ROR( uint16_t addr ) {
|
||||
dbgPrintf("ROR ");
|
||||
|
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@ -197,14 +168,6 @@ INSTR void ROR( uint16_t addr ) {
|
|||
_ROR(addr);
|
||||
#endif
|
||||
}
|
||||
INSTR void ROR_zp( uint16_t addr ) {
|
||||
dbgPrintf("ROR ");
|
||||
disPrintf(disassembly.inst, "ROR");
|
||||
|
||||
#ifndef DISASSEMBLER
|
||||
_ROR_zp(addr);
|
||||
#endif
|
||||
}
|
||||
INSTR void RORA() {
|
||||
dbgPrintf("ROR ");
|
||||
disPrintf(disassembly.inst, "ROR");
|
||||
|
|
|
|||
|
|
@ -88,15 +88,6 @@ INSTR void TRB( uint16_t addr ) {
|
|||
WRLOMEM[addr] &= ~m6502.A;
|
||||
#endif
|
||||
}
|
||||
INSTR void TRB_zp( uint16_t addr ) {
|
||||
dbgPrintf("TRB(%02X) ", src);
|
||||
disPrintf(disassembly.inst, "TRB");
|
||||
|
||||
#ifndef DISASSEMBLER
|
||||
set_flags_Z( WRZEROPG[addr] & m6502.A );
|
||||
WRZEROPG[addr] &= ~m6502.A;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
TSB - Test and Set Bits
|
||||
|
|
@ -127,15 +118,6 @@ INSTR void TSB( uint16_t addr ) {
|
|||
WRLOMEM[addr] |= m6502.A;
|
||||
#endif
|
||||
}
|
||||
INSTR void TSB_zp( uint16_t addr ) {
|
||||
dbgPrintf("TSB(%02X) ", src);
|
||||
disPrintf(disassembly.inst, "TSB");
|
||||
|
||||
#ifndef DISASSEMBLER
|
||||
set_flags_Z( WRZEROPG[addr] & m6502.A );
|
||||
WRZEROPG[addr] |= m6502.A;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
CMP Compare Memory with Accumulator
|
||||
|
|
|
|||
|
|
@ -39,18 +39,6 @@
|
|||
absolute,X INC oper,X FE 3 7
|
||||
**/
|
||||
#ifndef DISASSEMBLER
|
||||
INSTR void _INC_zp( uint16_t addr ) {
|
||||
set_flags_NZ( ++(WRZEROPG[addr]) );
|
||||
}
|
||||
#endif
|
||||
INSTR void INC_zp( uint16_t addr ) {
|
||||
disPrintf(disassembly.inst, "INC");
|
||||
|
||||
#ifndef DISASSEMBLER
|
||||
_INC_zp(addr);
|
||||
#endif
|
||||
}
|
||||
#ifndef DISASSEMBLER
|
||||
INSTR void _INC( uint16_t addr ) {
|
||||
set_flags_NZ( ++(WRLOMEM[addr]) );
|
||||
}
|
||||
|
|
@ -137,20 +125,10 @@ INSTR void INA(void) {
|
|||
absolute,X DEC oper,X DE 3 7
|
||||
**/
|
||||
#ifndef DISASSEMBLER
|
||||
INSTR void _DEC_zp( uint16_t addr ) {
|
||||
set_flags_NZ( --(WRZEROPG[addr]) );
|
||||
}
|
||||
INSTR void _DEC( uint16_t addr ) {
|
||||
set_flags_NZ( --(WRLOMEM[addr]) );
|
||||
}
|
||||
#endif
|
||||
INSTR void DEC_zp( uint16_t addr ) {
|
||||
disPrintf(disassembly.inst, "DEC");
|
||||
|
||||
#ifndef DISASSEMBLER
|
||||
_DEC_zp(addr);
|
||||
#endif
|
||||
}
|
||||
INSTR void DEC( uint16_t addr ) {
|
||||
disPrintf(disassembly.inst, "DEC");
|
||||
|
||||
|
|
|
|||
|
|
@ -117,12 +117,6 @@ INSTR void STR( uint16_t addr, uint8_t src ) {
|
|||
_memwrite(addr, src);
|
||||
#endif
|
||||
}
|
||||
INSTR void STR_zp( uint8_t addr, uint8_t src ) {
|
||||
dbgPrintf("STR [%04X], %02X ", addr, src );
|
||||
#ifndef DISASSEMBLER
|
||||
_memwrite8_zp(addr, src);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
STA Store Accumulator in Memory
|
||||
|
|
@ -147,13 +141,6 @@ INSTR void STA( uint16_t addr ) {
|
|||
STR(addr, m6502.A);
|
||||
#endif
|
||||
}
|
||||
INSTR void STA_zp( uint8_t addr ) {
|
||||
dbgPrintf("STA ");
|
||||
disPrintf(disassembly.inst, "STA");
|
||||
#ifndef DISASSEMBLER
|
||||
STR_zp(addr, m6502.A);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
STX Store Index X in Memory
|
||||
|
|
@ -174,13 +161,6 @@ INSTR void STX( uint16_t addr ) {
|
|||
STR(addr, m6502.X);
|
||||
#endif
|
||||
}
|
||||
INSTR void STX_zp( uint8_t addr ) {
|
||||
dbgPrintf("STX ");
|
||||
disPrintf(disassembly.inst, "STX");
|
||||
#ifndef DISASSEMBLER
|
||||
STR_zp(addr, m6502.X);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
STY Sore Index Y in Memory
|
||||
|
|
@ -201,13 +181,6 @@ INSTR void STY( uint16_t addr ) {
|
|||
STR(addr, m6502.Y);
|
||||
#endif
|
||||
}
|
||||
INSTR void STY_zp( uint8_t addr ) {
|
||||
dbgPrintf("STY ");
|
||||
disPrintf(disassembly.inst, "STY");
|
||||
#ifndef DISASSEMBLER
|
||||
STR_zp(addr, m6502.Y);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
STZ Store Zero (0) in Memory
|
||||
|
|
@ -229,13 +202,6 @@ INSTR void STZ( uint16_t addr ) {
|
|||
STR(addr, 0);
|
||||
#endif
|
||||
}
|
||||
INSTR void STZ_zp( uint8_t addr ) {
|
||||
dbgPrintf("STZ ");
|
||||
disPrintf(disassembly.inst, "STZ");
|
||||
#ifndef DISASSEMBLER
|
||||
STR_zp(addr, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif // __6502_INSTR_LOAD_STORE_H__
|
||||
|
||||
|
|
|
|||
|
|
@ -193,7 +193,7 @@ INSTR void SEI(void) {
|
|||
#define RMB(n) INSTR void RMB##n( uint8_t zpg ) { \
|
||||
dbgPrintf("RMB"#n" "); \
|
||||
disPrintf(disassembly.inst, "RMB"#n); \
|
||||
WRZEROPG[zpg] &= ~(1 << n); \
|
||||
WRLOMEM[zpg] &= ~(1 << n); \
|
||||
}
|
||||
#else
|
||||
#define RMB(n) INSTR void RMB##n( uint8_t zpg ) { \
|
||||
|
|
@ -216,7 +216,7 @@ INSTR void SEI(void) {
|
|||
#define SMB(n) INSTR void SMB##n( uint8_t zpg ) { \
|
||||
dbgPrintf("SMB"#n" "); \
|
||||
disPrintf(disassembly.inst, "SMB"#n); \
|
||||
WRZEROPG[zpg] |= (1 << n); \
|
||||
WRLOMEM[zpg] |= (1 << n); \
|
||||
}
|
||||
#else
|
||||
#define SMB(n) INSTR void SMB##n( uint8_t zpg ) { \
|
||||
|
|
|
|||
|
|
@ -44,10 +44,6 @@ INSTR void _ASL( uint16_t addr ) {
|
|||
m6502.C = _memread(addr) & 0x80;
|
||||
set_flags_NZ( WRLOMEM[addr] <<= 1 );
|
||||
}
|
||||
INSTR void _ASL_zp( uint16_t addr ) {
|
||||
m6502.C = _memread(addr) & 0x80;
|
||||
set_flags_NZ( WRZEROPG[addr] <<= 1 );
|
||||
}
|
||||
#endif
|
||||
INSTR void ASL( uint16_t addr ) {
|
||||
dbgPrintf("ASL ");
|
||||
|
|
@ -57,14 +53,6 @@ INSTR void ASL( uint16_t addr ) {
|
|||
_ASL(addr);
|
||||
#endif
|
||||
}
|
||||
INSTR void ASL_zp( uint16_t addr ) {
|
||||
dbgPrintf("ASL ");
|
||||
disPrintf(disassembly.inst, "ASL");
|
||||
|
||||
#ifndef DISASSEMBLER
|
||||
_ASL_zp(addr);
|
||||
#endif
|
||||
}
|
||||
INSTR void ASLA(void) {
|
||||
dbgPrintf("ASL ");
|
||||
disPrintf(disassembly.inst, "ASL");
|
||||
|
|
@ -98,15 +86,6 @@ INSTR void LSR( uint16_t addr ) {
|
|||
set_flags_NZ( WRLOMEM[addr] >>= 1 );
|
||||
#endif
|
||||
}
|
||||
INSTR void LSR_zp( uint16_t addr ) {
|
||||
dbgPrintf("LSR ");
|
||||
disPrintf(disassembly.inst, "LSR");
|
||||
|
||||
#ifndef DISASSEMBLER
|
||||
m6502.C = WRZEROPG[addr] & 1;
|
||||
set_flags_NZ( WRZEROPG[addr] >>= 1 );
|
||||
#endif
|
||||
}
|
||||
INSTR void LSRA(void) {
|
||||
dbgPrintf("LSR ");
|
||||
disPrintf(disassembly.inst, "LSR");
|
||||
|
|
@ -138,12 +117,6 @@ INSTR void _ROL( uint16_t addr ) {
|
|||
WRLOMEM[addr] <<= 1;
|
||||
set_flags_NZ( WRLOMEM[addr] |= C );
|
||||
}
|
||||
INSTR void _ROL_zp( uint16_t addr ) {
|
||||
uint8_t C = m6502.C != 0;
|
||||
m6502.C = WRZEROPG[addr] & 0x80;
|
||||
WRZEROPG[addr] <<= 1;
|
||||
set_flags_NZ( WRZEROPG[addr] |= C );
|
||||
}
|
||||
#endif
|
||||
INSTR void ROL( uint16_t addr ) {
|
||||
dbgPrintf("ROL ");
|
||||
|
|
@ -153,14 +126,6 @@ INSTR void ROL( uint16_t addr ) {
|
|||
_ROL(addr);
|
||||
#endif
|
||||
}
|
||||
INSTR void ROL_zp( uint16_t addr ) {
|
||||
dbgPrintf("ROL ");
|
||||
disPrintf(disassembly.inst, "ROL");
|
||||
|
||||
#ifndef DISASSEMBLER
|
||||
_ROL_zp(addr);
|
||||
#endif
|
||||
}
|
||||
INSTR void ROLA(void) {
|
||||
dbgPrintf("ROL ");
|
||||
disPrintf(disassembly.inst, "ROL");
|
||||
|
|
@ -194,12 +159,6 @@ INSTR void _ROR( uint16_t addr ) {
|
|||
WRLOMEM[addr] >>= 1;
|
||||
set_flags_NZ( WRLOMEM[addr] |= C << 7 );
|
||||
}
|
||||
INSTR void _ROR_zp( uint16_t addr ) {
|
||||
uint8_t C = m6502.C != 0;
|
||||
m6502.C = WRZEROPG[addr] & 1;
|
||||
WRZEROPG[addr] >>= 1;
|
||||
set_flags_NZ( WRZEROPG[addr] |= C << 7 );
|
||||
}
|
||||
#endif
|
||||
INSTR void ROR( uint16_t addr ) {
|
||||
dbgPrintf("ROR ");
|
||||
|
|
@ -209,14 +168,6 @@ INSTR void ROR( uint16_t addr ) {
|
|||
_ROR(addr);
|
||||
#endif
|
||||
}
|
||||
INSTR void ROR_zp( uint16_t addr ) {
|
||||
dbgPrintf("ROR ");
|
||||
disPrintf(disassembly.inst, "ROR");
|
||||
|
||||
#ifndef DISASSEMBLER
|
||||
_ROR_zp(addr);
|
||||
#endif
|
||||
}
|
||||
INSTR void RORA(void) {
|
||||
dbgPrintf("ROR ");
|
||||
disPrintf(disassembly.inst, "ROR");
|
||||
|
|
|
|||
|
|
@ -77,7 +77,7 @@ MEMcfg_t MEMcfg = INIT_MEMCFG;
|
|||
MEMcfg_t newMEMcfg = INIT_MEMCFG;
|
||||
|
||||
|
||||
uint8_t * shadowZPSTCKMEM = Apple2_64K_MEM;
|
||||
const uint8_t * const shadowZPSTCKMEM = Apple2_64K_MEM;
|
||||
const uint8_t * currentZPSTCKMEM = Apple2_64K_RAM;
|
||||
const uint8_t * const shadowLowMEM = Apple2_64K_MEM + 0x200;
|
||||
const uint8_t * currentLowRDMEM = Apple2_64K_RAM + 0x200;
|
||||
|
|
@ -1008,9 +1008,6 @@ INLINE uint8_t check_mem_wr_bp(uint16_t addr) {
|
|||
/**
|
||||
Naive implementation of RAM read from address
|
||||
**/
|
||||
INLINE uint8_t memread8_zp( uint16_t addr ) {
|
||||
return shadowZPSTCKMEM[addr];
|
||||
}
|
||||
INLINE uint8_t memread8_low( uint16_t addr ) {
|
||||
return Apple2_64K_MEM[addr];
|
||||
}
|
||||
|
|
@ -1021,17 +1018,11 @@ INLINE uint8_t memread8( uint16_t addr ) {
|
|||
if (addr >= 0xC000) {
|
||||
return memread8_high(addr);
|
||||
}
|
||||
if (addr >= 0x200) {
|
||||
return memread8_low(addr);
|
||||
}
|
||||
return memread8_zp(addr);
|
||||
return memread8_low(addr);
|
||||
}
|
||||
/**
|
||||
Naive implementation of RAM read from address
|
||||
**/
|
||||
INLINE uint16_t memread16_zp( uint16_t addr ) {
|
||||
return * (uint16_t*) ( shadowZPSTCKMEM + addr );
|
||||
}
|
||||
INLINE uint16_t memread16_low( uint16_t addr ) {
|
||||
return * (uint16_t*) ( Apple2_64K_MEM + addr );
|
||||
|
||||
|
|
@ -1063,15 +1054,12 @@ INLINE uint8_t _memread( uint16_t addr ) {
|
|||
if (addr < 0xC100) {
|
||||
return ioRead(addr);
|
||||
}
|
||||
|
||||
// return memread8_paged(addr);
|
||||
return memread8_high(addr);
|
||||
}
|
||||
if (addr >= 0x200) {
|
||||
return memread8_low(addr);
|
||||
}
|
||||
|
||||
// return memread8_paged(addr);
|
||||
return memread8_zp(addr);
|
||||
return memread8_low(addr);
|
||||
|
||||
// return memread8(addr);
|
||||
}
|
||||
|
|
@ -1086,12 +1074,8 @@ INLINE uint8_t _memread_dis( uint16_t addr ) {
|
|||
// return memread8_paged(addr);
|
||||
return memread8_high(addr);
|
||||
}
|
||||
if (addr >= 0x200) {
|
||||
return memread8_low(addr);
|
||||
}
|
||||
|
||||
// return memread8_paged(addr);
|
||||
return memread8_zp(addr);
|
||||
return memread8_low(addr);
|
||||
|
||||
// return memread8(addr);
|
||||
}
|
||||
|
|
@ -1117,9 +1101,6 @@ INLINE uint8_t _memread_dis( uint16_t addr ) {
|
|||
Naive implementation of RAM write to address
|
||||
**/
|
||||
|
||||
INLINE void _memwrite8_zp( uint16_t addr, uint8_t data ) {
|
||||
shadowZPSTCKMEM[addr] = data;
|
||||
}
|
||||
INLINE void _memwrite8_low( uint16_t addr, uint8_t data ) {
|
||||
if ((addr >= 0x400) && (addr < 0x800)) {
|
||||
if ((data == 0x00) || (data == 0xFF)) {
|
||||
|
|
@ -1152,13 +1133,9 @@ INLINE void _memwrite( uint16_t addr, uint8_t data ) {
|
|||
memwrite8_high(addr, data);
|
||||
}
|
||||
}
|
||||
else if (addr >= 0x200) {
|
||||
// RAM
|
||||
memwrite8_low(addr, data);
|
||||
}
|
||||
else {
|
||||
// RAM
|
||||
memwrite8_zp(addr, data);
|
||||
memwrite8_low(addr, data);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1373,13 +1350,13 @@ INLINE uint8_t _addr_zp_dis(void) {
|
|||
return _fetch_dis();
|
||||
}
|
||||
INLINE uint8_t _src_zp(void) {
|
||||
return memread8(_addr_zp());
|
||||
return memread8_low(_addr_zp());
|
||||
}
|
||||
INLINE uint8_t _src_zp_dbg(void) {
|
||||
return _memread_dbg(_addr_zp_dbg());
|
||||
}
|
||||
INLINE uint8_t _src_zp_dis(void) {
|
||||
return memread8(_addr_zp_dis());
|
||||
return memread8_low(_addr_zp_dis());
|
||||
}
|
||||
//INLINE uint8_t * dest_zp() {
|
||||
// return WRLOMEM + addr_zp();
|
||||
|
|
@ -1537,13 +1514,13 @@ INLINE uint8_t _addr_zp_X_dis(void) {
|
|||
return _fetch_dis() + m6502.X;
|
||||
}
|
||||
INLINE uint8_t _src_zp_X(void) {
|
||||
return memread8(_addr_zp_X());
|
||||
return memread8_low(_addr_zp_X());
|
||||
}
|
||||
INLINE uint8_t _src_zp_X_dbg(void) {
|
||||
return _memread_dbg(_addr_zp_X());
|
||||
}
|
||||
INLINE uint8_t _src_zp_X_dis(void) {
|
||||
return memread8(_addr_zp_X_dis());
|
||||
return memread8_low(_addr_zp_X_dis());
|
||||
}
|
||||
//INLINE uint8_t * dest_zp_X() {
|
||||
// return WRLOMEM + addr_zp_X();
|
||||
|
|
@ -1568,13 +1545,13 @@ INLINE uint8_t _addr_zp_Y_dis(void) {
|
|||
return _fetch_dis() + m6502.Y;
|
||||
}
|
||||
INLINE uint8_t _src_zp_Y(void) {
|
||||
return memread8(_addr_zp_Y());
|
||||
return memread8_low(_addr_zp_Y());
|
||||
}
|
||||
INLINE uint8_t _src_zp_Y_dbg(void) {
|
||||
return _memread_dbg(_addr_zp_Y());
|
||||
}
|
||||
INLINE uint8_t _src_zp_Y_dis(void) {
|
||||
return memread8(_addr_zp_Y_dis());
|
||||
return memread8_low(_addr_zp_Y_dis());
|
||||
}
|
||||
//INLINE uint8_t * dest_zp_Y() {
|
||||
// return WRLOMEM + addr_zp_Y();
|
||||
|
|
@ -1586,7 +1563,7 @@ void auxMemorySelect( MEMcfg_t newMEMcfg ) {
|
|||
uint8_t * newWriteMEM = currentLowWRMEM;
|
||||
|
||||
// TODO: Check if this is supposed to be the opposite
|
||||
// if ( newMEMcfg.is_80STORE ) {
|
||||
if ( newMEMcfg.is_80STORE ) {
|
||||
if ( newMEMcfg.RD_AUX_MEM ) {
|
||||
newReadMEM = Apple2_64K_AUX + 0x200;
|
||||
}
|
||||
|
|
@ -1600,11 +1577,11 @@ void auxMemorySelect( MEMcfg_t newMEMcfg ) {
|
|||
else {
|
||||
newWriteMEM = Apple2_64K_RAM;
|
||||
}
|
||||
// }
|
||||
// else {
|
||||
// newReadMEM = Apple2_64K_RAM + 0x200;
|
||||
// newWriteMEM = Apple2_64K_RAM;
|
||||
// }
|
||||
}
|
||||
else {
|
||||
newReadMEM = Apple2_64K_RAM + 0x200;
|
||||
newWriteMEM = Apple2_64K_RAM;
|
||||
}
|
||||
|
||||
|
||||
// save old content to shadow memory
|
||||
|
|
@ -1750,10 +1727,10 @@ void CxMemorySelect( MEMcfg_t newMEMcfg ) {
|
|||
void resetMemory(void) {
|
||||
newMEMcfg = initMEMcfg;
|
||||
|
||||
WRZEROPG = Apple2_64K_MEM; // for Write $0000 - $0200 (shadow memory)
|
||||
WRLOMEM = Apple2_64K_MEM; // for Write $0200 - $BFFF (shadow memory)
|
||||
WRD0MEM = Apple2_Dummy_RAM; // for writing $D000 - $DFFF
|
||||
WRHIMEM = Apple2_Dummy_RAM; // for writing $E000 - $FFFF
|
||||
WRZEROPG= Apple2_64K_MEM; // for Write $0000 - $0200 (shadow memory)
|
||||
WRLOMEM = Apple2_64K_MEM; // for Write $0200 - $BFFF (shadow memory)
|
||||
WRD0MEM = Apple2_Dummy_RAM; // for writing $D000 - $DFFF
|
||||
WRHIMEM = Apple2_Dummy_RAM; // for writing $E000 - $FFFF
|
||||
|
||||
auxMemorySelect(MEMcfg);
|
||||
CxMemorySelect(MEMcfg);
|
||||
|
|
@ -1821,8 +1798,7 @@ void setIO ( uint16_t ioaddr, uint8_t val ) {
|
|||
}
|
||||
|
||||
uint8_t getMEM ( uint16_t addr ) {
|
||||
return memread8(addr);
|
||||
// return Apple2_64K_MEM[addr];
|
||||
return Apple2_64K_MEM[addr];
|
||||
}
|
||||
|
||||
uint16_t getMEM16 ( uint16_t addr ) {
|
||||
|
|
|
|||
|
|
@ -414,7 +414,6 @@ INLINE uint16_t memread16( uint16_t addr );
|
|||
INLINE uint8_t _memread( uint16_t addr );
|
||||
INLINE uint8_t _memread_dbg( uint16_t addr );
|
||||
INLINE uint8_t _memread_dis( uint16_t addr );
|
||||
INLINE void _memwrite8_zp( uint16_t addr, uint8_t data );
|
||||
INLINE void _memwrite8_low( uint16_t addr, uint8_t data );
|
||||
INLINE void _memwrite8_bank( uint16_t addr, uint8_t data );
|
||||
INLINE void _memwrite8_high( uint16_t addr, uint8_t data );
|
||||
|
|
@ -498,7 +497,6 @@ INLINE uint8_t _src_zp_Y_dis(void);
|
|||
#define fetch() _fetch_dis()
|
||||
#define fetch16() _fetch16_dis()
|
||||
#define memread(addr) _memread_dis(addr)
|
||||
#define memwrite8_zp(addr,data) // do not write anything into the memory while disassembling
|
||||
#define memwrite8_low(addr,data) // do not write anything into the memory while disassembling
|
||||
#define memwrite8_bank(addr,data) // do not write anything into the memory while disassembling
|
||||
#define memwrite8_high(addr,data) // do not write anything into the memory while disassembling
|
||||
|
|
@ -533,7 +531,6 @@ INLINE uint8_t _src_zp_Y_dis(void);
|
|||
#define fetch() _fetch()
|
||||
#define fetch16() _fetch16()
|
||||
#define memread(addr) _memread_dbg(addr)
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#define memwrite8_zp(addr,data) _memwrite8_zp(addr,data)
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#define memwrite8_low(addr,data) _memwrite8_low(addr,data)
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#define memwrite8_bank(addr,data) _memwrite8_bank(addr,data)
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#define memwrite8_high(addr,data) _memwrite8_high(addr,data)
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@ -568,7 +565,6 @@ INLINE uint8_t _src_zp_Y_dis(void);
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#define fetch() _fetch()
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#define fetch16() _fetch16()
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#define memread(addr) _memread(addr)
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#define memwrite8_zp(addr,data) _memwrite8_zp(addr,data)
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#define memwrite8_low(addr,data) _memwrite8_low(addr,data)
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#define memwrite8_bank(addr,data) _memwrite8_bank(addr,data)
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#define memwrite8_high(addr,data) _memwrite8_high(addr,data)
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user