mirror of https://github.com/trudnai/Steve2.git
84 lines
2.3 KiB
C
84 lines
2.3 KiB
C
//
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// main.c
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// 6502
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//
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// Created by Tamas Rudnai on 7/14/19.
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// Copyright © 2019 GameAlloy. All rights reserved.
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//
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#ifndef __6502_INSTR_LOGIC_H__
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#define __6502_INSTR_LOGIC_H__
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/**
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ORA OR Memory with Accumulator
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A OR M -> A N Z C I D V
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+ + - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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immidiate ORA #oper 09 2 2
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zeropage ORA oper 05 2 3
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zeropage,X ORA oper,X 15 2 4
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absolute ORA oper 0D 3 4
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absolute,X ORA oper,X 1D 3 4*
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absolute,Y ORA oper,Y 19 3 4*
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(indirect,X) ORA (oper,X) 01 2 6
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(indirect),Y ORA (oper),Y 11 2 5*
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**/
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INLINE void ORA( uint8_t src ) {
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dbgPrintf("ORA(%02X) ", src);
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disPrintf(disassembly.inst, "ORA");
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set_flags_NZ( m6502.A |= src );
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}
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/**
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AND AND Memory with Accumulator
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A AND M -> A N Z C I D V
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+ + - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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immidiate AND #oper 29 2 2
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zeropage AND oper 25 2 3
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zeropage,X AND oper,X 35 2 4
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absolute AND oper 2D 3 4
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absolute,X AND oper,X 3D 3 4*
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absolute,Y AND oper,Y 39 3 4*
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(indirect,X) AND (oper,X) 21 2 6
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(indirect),Y AND (oper),Y 31 2 5*
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**/
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INLINE void AND( uint8_t src ) {
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dbgPrintf("AND(%02X) ", src);
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disPrintf(disassembly.inst, "AND");
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set_flags_NZ( m6502.A &= src );
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}
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/**
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EOR Exclusive-OR Memory with Accumulator
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A EOR M -> A N Z C I D V
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+ + - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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immidiate EOR #oper 49 2 2
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zeropage EOR oper 45 2 3
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zeropage,X EOR oper,X 55 2 4
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absolute EOR oper 4D 3 4
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absolute,X EOR oper,X 5D 3 4*
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absolute,Y EOR oper,Y 59 3 4*
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(indirect,X) EOR (oper,X) 41 2 6
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(indirect),Y EOR (oper),Y 51 2 5*
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**/
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INLINE void EOR( uint8_t src ) {
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dbgPrintf("EOR(%02X) ", src);
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disPrintf(disassembly.inst, "EOR");
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set_flags_NZ( m6502.A ^= src );
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}
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#endif // __6502_INSTR_LOGIC_H__
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