mirror of https://github.com/trudnai/Steve2.git
126 lines
2.7 KiB
C
126 lines
2.7 KiB
C
//
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// main.c
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// 6502
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//
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// Created by Tamas Rudnai on 7/14/19.
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// Copyright © 2019 GameAlloy. All rights reserved.
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//
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#ifndef __6502_INSTR_SET_CLR_H__
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#define __6502_INSTR_SET_CLR_H__
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/**
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CLC Clear Carry Flag
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0 -> C N Z C I D V
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- - 0 - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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implied CLC 18 1 2
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**/
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INLINE void CLC() {
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dbgPrintf("CLC ");
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disPrintf(disassembly.inst, "CLC");
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m6502.C = 0;
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}
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/**
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CLD Clear Decimal Mode
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0 -> D N Z C I D V
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- - - - 0 -
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addressing assembler opc bytes cyles
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--------------------------------------------
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implied CLD D8 1 2
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**/
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INLINE void CLD() {
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dbgPrintf("CLD ");
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disPrintf(disassembly.inst, "CLD");
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m6502.D = 0;
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}
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/**
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CLI Clear Interrupt Disable Bit
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0 -> I N Z C I D V
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- - - 0 - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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implied CLI 58 1 2
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**/
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INLINE void CLI() {
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dbgPrintf("CLI ");
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disPrintf(disassembly.inst, "CLI");
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m6502.I = 0;
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}
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/**
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CLV Clear Overflow Flag
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0 -> V N Z C I D V
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- - - - - 0
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addressing assembler opc bytes cyles
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--------------------------------------------
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implied CLV B8 1 2
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**/
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INLINE void CLV() {
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dbgPrintf("CLV ");
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disPrintf(disassembly.inst, "CLV");
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m6502.V = 0;
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}
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/**
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SEC Set Carry Flag
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1 -> C N Z C I D V
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- - 1 - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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implied SEC 38 1 2
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**/
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INLINE void SEC() {
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dbgPrintf("SEC ");
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disPrintf(disassembly.inst, "SEC");
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m6502.C = 1;
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}
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/**
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SED Set Decimal Flag
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1 -> D N Z C I D V
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- - - - 1 -
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addressing assembler opc bytes cyles
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--------------------------------------------
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implied SED F8 1 2
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**/
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INLINE void SED() {
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dbgPrintf("SED ");
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disPrintf(disassembly.inst, "SED");
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m6502.D = 1;
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}
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/**
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SEI Set Interrupt Disable Status
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1 -> I N Z C I D V
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- - - 1 - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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implied SEI 78 1 2
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**/
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INLINE void SEI() {
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dbgPrintf("SEI ");
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disPrintf(disassembly.inst, "SEI");
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m6502.I = 1;
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}
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#endif // __6502_INSTR_SET_CLR_H__
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