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345 lines
8.5 KiB
C
345 lines
8.5 KiB
C
//
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// main.c
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// 6502
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//
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// Created by Tamas Rudnai on 7/14/19.
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// Copyright © 2019, 2020 Tamas Rudnai. All rights reserved.
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//
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// This file is part of Steve ][ -- The Apple ][ Emulator.
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//
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// Steve ][ is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// Steve ][ is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with Steve ][. If not, see <https://www.gnu.org/licenses/>.
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//
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#ifndef __6502_INSTR_BRANCH_H__
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#define __6502_INSTR_BRANCH_H__
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#ifndef DISASSEMBLER
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INSTR void _BRA( int8_t reladdr ) {
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uint8_t pg = m6502.PC >> 8;
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m6502.PC += reladdr;
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m6502.clkfrm += m6502.PC >> 8 == pg ? 1 : 2;
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#ifdef DEBUG
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if ( reladdr == -2 ) {
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dbgPrintf2("Infinite Loop at %04X!\n", m6502.PC);
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}
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#endif
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dbgPrintf("BRA %04X ", m6502.PC);
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}
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#endif // DISASSEMBLER
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/**
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BRA Branch Unconditionally
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addressing assembler opc bytes cyles
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--------------------------------------------
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relative BRA oper 90 2 2**
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**/
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INSTR void BRA( int8_t reladdr ) {
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dbgPrintf("BRA ");
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disPrintf(disassembly.inst, "BRA");
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#ifndef DISASSEMBLER
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_BRA( reladdr );
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#endif
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}
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/**
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BCC Branch on Carry Clear
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branch on C = 0 N Z C I D V
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- - - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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relative BCC oper 90 2 2**
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**/
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INSTR void BCC( int8_t reladdr ) {
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dbgPrintf("BCC ");
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disPrintf(disassembly.inst, "BCC");
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#ifndef DISASSEMBLER
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if ( ! m6502.C ) {
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_BRA( reladdr );
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}
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else {
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dbgPrintf("-no-");
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}
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#endif
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}
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/**
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BCS Branch on Carry Set
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branch on C = 1 N Z C I D V
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- - - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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relative BCS oper B0 2 2**
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**/
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INSTR void BCS( int8_t reladdr ) {
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dbgPrintf("BCS ");
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disPrintf(disassembly.inst, "BCS");
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#ifndef DISASSEMBLER
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if ( m6502.C ) {
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_BRA( reladdr );
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}
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else {
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dbgPrintf("-no-");
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}
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#endif
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}
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/**
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BNE Branch on Result not Zero
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branch on Z = 0 N Z C I D V
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- - - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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relative BNE oper D0 2 2**
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**/
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INSTR void BNE( int8_t reladdr ) {
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dbgPrintf("BNE ");
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disPrintf(disassembly.inst, "BNE");
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#ifndef DISASSEMBLER
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if ( ! m6502.Z ) {
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_BRA( reladdr );
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}
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else {
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dbgPrintf("-no-");
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}
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#endif
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}
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/**
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BEQ Branch on Result Zero
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branch on Z = 1 N Z C I D V
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- - - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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relative BEQ oper F0 2 2**
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**/
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INSTR void BEQ( int8_t reladdr ) {
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dbgPrintf("BEQ ");
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disPrintf(disassembly.inst, "BEQ");
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#ifndef DISASSEMBLER
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if ( m6502.Z ) {
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_BRA( reladdr );
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}
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else {
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dbgPrintf("-no-");
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}
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#endif
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}
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/**
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BPL Branch on Result Plus
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branch on N = 0 N Z C I D V
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- - - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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relative BPL oper 10 2 2**
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**/
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INSTR void BPL( int8_t reladdr ) {
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dbgPrintf("BPL ");
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disPrintf(disassembly.inst, "BPL");
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#ifndef DISASSEMBLER
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if ( ! m6502.N ) {
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_BRA( reladdr );
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}
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else {
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dbgPrintf("-no-");
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}
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#endif
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}
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/**
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BMI Branch on Result Minus
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branch on N = 1 N Z C I D V
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- - - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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relative BMI oper 30 2 2**
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**/
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INSTR void BMI( int8_t reladdr ) {
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dbgPrintf("BMI ");
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disPrintf(disassembly.inst, "BMI");
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#ifndef DISASSEMBLER
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if ( m6502.N ) {
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_BRA( reladdr );
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}
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else {
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dbgPrintf("-no-");
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}
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#endif
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}
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/**
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BVC Branch on Overflow Clear
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branch on V = 0 N Z C I D V
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- - - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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relative BVC oper 50 2 2**
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**/
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INSTR void BVC( int8_t reladdr ) {
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dbgPrintf("BVC ");
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disPrintf(disassembly.inst, "BVC");
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#ifndef DISASSEMBLER
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if ( ! m6502.V ) {
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_BRA( reladdr );
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}
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else {
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dbgPrintf("-no-");
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}
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#endif
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}
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/**
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BVS Branch on Overflow Set
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branch on V = 1 N Z C I D V
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- - - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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relative BVC oper 70 2 2**
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**/
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INSTR void BVS( int8_t reladdr ) {
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dbgPrintf("BVS ");
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disPrintf(disassembly.inst, "BVS");
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#ifndef DISASSEMBLER
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if ( m6502.V ) {
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_BRA( reladdr );
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}
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else {
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dbgPrintf("-no-");
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}
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#endif
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}
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/**
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BBR BBS - Branch on Bit Reset or Set
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BBR and BBS test the specified zero page location and branch if the specified bit is clear (BBR) or set (BBS).
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Note that as with TRB, the term reset in BBR is used to mean clear.
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On the 6502 and 65C02, bit 7 is typically the most convenient bit to use for I/O and software flags because
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it can be tested by several instructions, such as BIT and LDA. BBR and BBS can test any of the 8 bits without
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affecting any flags or using any registers. Unlike other branch instructions, BBR and BBS always take the same
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number of cycles (five) whether the branch is taken or not. It is often useful to test bit 0, for example, to test
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whether a byte is even or odd. However, the usefulness of BBR and BBS is somewhat limited for a couple of reasons.
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First, there is only a single addressing mode for these instructions -- no indexing by X or Y, for instance.
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Second, they are restricted to zero page locations. For software flags this may be just fine, but it may not be very
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convenient (or cost effective) to add any additional address decoding hardware that may be necessary to
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map I/O locations to the zero page.
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The addressing mode is a combination of zero page addressing and relative addressing -- really just a juxtaposition of the two.
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The bit to test is typically specified as part of the instruction name rather than the operand, i.e.
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Flags affected: none
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OP LEN CYC MODE FLAGS SYNTAX
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-- --- --- ---- ----- ------
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0F 3 5 zp,rel ........ BBR0 $12,LABEL
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1F 3 5 zp,rel ........ BBR1 $12,LABEL
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2F 3 5 zp,rel ........ BBR2 $12,LABEL
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3F 3 5 zp,rel ........ BBR3 $12,LABEL
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4F 3 5 zp,rel ........ BBR4 $12,LABEL
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5F 3 5 zp,rel ........ BBR5 $12,LABEL
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6F 3 5 zp,rel ........ BBR6 $12,LABEL
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7F 3 5 zp,rel ........ BBR7 $12,LABEL
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8F 3 5 zp,rel ........ BBS0 $12,LABEL
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9F 3 5 zp,rel ........ BBS1 $12,LABEL
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AF 3 5 zp,rel ........ BBS2 $12,LABEL
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BF 3 5 zp,rel ........ BBS3 $12,LABEL
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CF 3 5 zp,rel ........ BBS4 $12,LABEL
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DF 3 5 zp,rel ........ BBS5 $12,LABEL
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EF 3 5 zp,rel ........ BBS6 $12,LABEL
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FF 3 5 zp,rel ........ BBS7 $12,LABEL
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**/
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#ifndef DISASSEMBLER
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#define BBR(n) INSTR void BBR##n( uint8_t src, int8_t reladdr ) { \
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dbgPrintf("BBR"#n" "); \
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disPrintf(disassembly.inst, "BBR"#n); \
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if ( ! (src & (1 << n) ) ) { \
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_BRA( reladdr ); \
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} \
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}
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#else
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#define BBR(n) INSTR void BBR##n( uint8_t src, int8_t reladdr ) { \
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dbgPrintf("BBR"#n" "); \
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disPrintf(disassembly.inst, "BBR"#n); \
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}
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#endif
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BBR(0)
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BBR(1)
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BBR(2)
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BBR(3)
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BBR(4)
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BBR(5)
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BBR(6)
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BBR(7)
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#ifndef DISASSEMBLER
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#define BBS(n) INSTR void BBS##n( uint8_t src, int8_t reladdr ) { \
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dbgPrintf("BBS"#n" "); \
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disPrintf(disassembly.inst, "BBS"#n); \
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if ( (src & (1 << n) ) ) { \
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_BRA( reladdr ); \
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} \
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}
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#else
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#define BBS(n) INSTR void BBS##n( uint8_t src, int8_t reladdr ) { \
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dbgPrintf("BBS"#n" "); \
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disPrintf(disassembly.inst, "BBS"#n); \
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}
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#endif
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BBS(0)
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BBS(1)
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BBS(2)
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BBS(3)
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BBS(4)
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BBS(5)
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BBS(6)
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BBS(7)
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#endif // __6502_INSTR_BRANCH_H__
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