mirror of https://github.com/trudnai/Steve2.git
79 lines
4.1 KiB
C
79 lines
4.1 KiB
C
//
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// 6502_und.h
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// A2Mac
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//
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// Created by Tamas Rudnai on 7/27/20.
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// Copyright © 2019, 2020 Tamas Rudnai. All rights reserved.
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//
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// This file is part of Steve ][ -- The Apple ][ Emulator.
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//
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// Steve ][ is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// Steve ][ is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with Steve ][. If not, see <https://www.gnu.org/licenses/>.
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//
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// Documentations:
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//
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// http://nesdev.com/6502_cpu.txt
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// http://www.oxyron.de/html/opcodes02.html
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// https://macgui.com/kb/article/46
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// https://www.masswerk.at/6502/6502_instruction_set.html
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//
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#ifndef _6502_C_Rockwell_h
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#define _6502_C_Rockwell_h
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// Additional Rockwell 65C02 and WDC 65C02 instructions
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// Four additional instructions and one additional addressing mode are available on 65C02s manufactured by Rockwell and WDC
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// BBR BBS - Branch on Bit Reset or Set
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case 0x0F: BBR0( src_zp(), rel_addr() ); return 5; // BBR0 zpg, rel
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case 0x1F: BBR1( src_zp(), rel_addr() ); return 5; // BBR1 zpg, rel
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case 0x2F: BBR2( src_zp(), rel_addr() ); return 5; // BBR2 zpg, rel
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case 0x3F: BBR3( src_zp(), rel_addr() ); return 5; // BBR3 zpg, rel
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case 0x4F: BBR4( src_zp(), rel_addr() ); return 5; // BBR4 zpg, rel
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case 0x5F: BBR5( src_zp(), rel_addr() ); return 5; // BBR5 zpg, rel
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case 0x6F: BBR6( src_zp(), rel_addr() ); return 5; // BBR6 zpg, rel
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case 0x7F: BBR7( src_zp(), rel_addr() ); return 5; // BBR7 zpg, rel
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case 0x8F: BBS0( src_zp(), rel_addr() ); return 5; // BBS0 zpg, rel
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case 0x9F: BBS1( src_zp(), rel_addr() ); return 5; // BBS1 zpg, rel
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case 0xAF: BBS2( src_zp(), rel_addr() ); return 5; // BBS2 zpg, rel
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case 0xBF: BBS3( src_zp(), rel_addr() ); return 5; // BBS3 zpg, rel
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case 0xCF: BBS4( src_zp(), rel_addr() ); return 5; // BBS4 zpg, rel
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case 0xDF: BBS5( src_zp(), rel_addr() ); return 5; // BBS5 zpg, rel
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case 0xEF: BBS6( src_zp(), rel_addr() ); return 5; // BBS6 zpg, rel
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case 0xFF: BBS7( src_zp(), rel_addr() ); return 5; // BBS7 zpg, rel
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// RMB SMB - Reset or Set Memory Bit
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case 0x07: RMB0( src_zp() ); return 5; // RMB0 zpg, rel
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case 0x17: RMB1( src_zp() ); return 5; // RMB1 zpg, rel
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case 0x27: RMB2( src_zp() ); return 5; // RMB2 zpg, rel
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case 0x37: RMB3( src_zp() ); return 5; // RMB3 zpg, rel
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case 0x47: RMB4( src_zp() ); return 5; // RMB4 zpg, rel
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case 0x57: RMB5( src_zp() ); return 5; // RMB5 zpg, rel
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case 0x67: RMB6( src_zp() ); return 5; // RMB6 zpg, rel
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case 0x77: RMB7( src_zp() ); return 5; // RMB7 zpg, rel
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case 0x87: SMB0( src_zp() ); return 5; // SMB0 zpg, rel
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case 0x97: SMB1( src_zp() ); return 5; // SMB1 zpg, rel
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case 0xA7: SMB2( src_zp() ); return 5; // SMB2 zpg, rel
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case 0xB7: SMB3( src_zp() ); return 5; // SMB3 zpg, rel
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case 0xC7: SMB4( src_zp() ); return 5; // SMB4 zpg, rel
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case 0xD7: SMB5( src_zp() ); return 5; // SMB5 zpg, rel
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case 0xE7: SMB6( src_zp() ); return 5; // SMB6 zpg, rel
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case 0xF7: SMB7( src_zp() ); return 5; // SMB7 zpg, rel
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#endif /* _6502_C_Rockwell_h */
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