mirror of https://github.com/trudnai/Steve2.git
240 lines
6.3 KiB
C
240 lines
6.3 KiB
C
//
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// main.c
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// 6502
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//
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// Created by Tamas Rudnai on 7/14/19.
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// Copyright © 2019, 2020 Tamas Rudnai. All rights reserved.
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//
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// This file is part of Steve ][ -- The Apple ][ Emulator.
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//
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// Steve ][ is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// Steve ][ is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with Steve ][. If not, see <https://www.gnu.org/licenses/>.
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//
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#ifndef __6502_INSTR_SET_CLR_H__
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#define __6502_INSTR_SET_CLR_H__
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/**
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CLC Clear Carry Flag
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0 -> C N Z C I D V
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- - 0 - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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implied CLC 18 1 2
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**/
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INSTR void CLC(void) {
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dbgPrintf("CLC ");
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disPrintf(disassembly.inst, "CLC");
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#ifndef DISASSEMBLER
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m6502.C = 0;
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#endif
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}
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/**
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CLD Clear Decimal Mode
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0 -> D N Z C I D V
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- - - - 0 -
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addressing assembler opc bytes cyles
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--------------------------------------------
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implied CLD D8 1 2
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**/
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INSTR void CLD(void) {
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dbgPrintf("CLD ");
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disPrintf(disassembly.inst, "CLD");
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#ifndef DISASSEMBLER
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m6502.D = 0;
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#endif
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}
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/**
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CLI Clear Interrupt Disable Bit
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0 -> I N Z C I D V
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- - - 0 - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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implied CLI 58 1 2
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**/
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INSTR void CLI(void) {
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dbgPrintf("CLI ");
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disPrintf(disassembly.inst, "CLI");
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#ifndef DISASSEMBLER
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m6502.I = 0;
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#endif
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}
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/**
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CLV Clear Overflow Flag
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0 -> V N Z C I D V
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- - - - - 0
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addressing assembler opc bytes cyles
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--------------------------------------------
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implied CLV B8 1 2
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**/
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INSTR void CLV(void) {
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dbgPrintf("CLV ");
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disPrintf(disassembly.inst, "CLV");
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#ifndef DISASSEMBLER
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m6502.V = 0;
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#endif
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}
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/**
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SEC Set Carry Flag
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1 -> C N Z C I D V
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- - 1 - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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implied SEC 38 1 2
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**/
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INSTR void SEC(void) {
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dbgPrintf("SEC ");
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disPrintf(disassembly.inst, "SEC");
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#ifndef DISASSEMBLER
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m6502.C = 1;
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#endif
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}
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/**
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SED Set Decimal Flag
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1 -> D N Z C I D V
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- - - - 1 -
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addressing assembler opc bytes cyles
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--------------------------------------------
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implied SED F8 1 2
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**/
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INSTR void SED(void) {
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dbgPrintf("SED ");
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disPrintf(disassembly.inst, "SED");
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#ifndef DISASSEMBLER
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m6502.D = 1;
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#endif
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}
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/**
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SEI Set Interrupt Disable Status
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1 -> I N Z C I D V
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- - - 1 - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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implied SEI 78 1 2
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**/
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INSTR void SEI(void) {
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dbgPrintf("SEI ");
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disPrintf(disassembly.inst, "SEI");
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#ifndef DISASSEMBLER
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m6502.I = 1;
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#endif
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}
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/**
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RMB SMB - Reset or Set Memory Bit
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RMB and SMB clear (RMB) or set (SMB) the specified bit in the specified zero page location,
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and can be used in conjuction with the BBR and BBS instructions. Again, note that as with BBR and TRB,
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the term reset in RMB is used to mean clear.
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The function of RMB and SMB is very similar to the function of TRB and TSB, except that RMB and SMB
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can clear or set only one zero page bit, whereas TRB and TSB can clear or set any number of bits. Also,
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only zero page addressing is available with RMB and SMB, whereas zero page and absolute addressing
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are available for both TRB and TSB. As a result, RMB and SMB do not offer much that isn't already available
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with TRB and TSB (which are available on 65C02s from all manufacturers). The main advantages are that
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RMB and SMB, unlike TRB and TSB, do not use the accumulator, leaving it available, and do not affect any flags.
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However, it is worth noting that it is rarely useful to preserve the value of the Z (zero) flag (the only flag affected by
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TRB and TSB), unlike other flags (such as the carry).
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Like BBR and BBS, the bit to test is typically specified as part of the instruction name rather than the operand, i.e.
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Flags affected: none
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OP LEN CYC MODE FLAGS SYNTAX
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-- --- --- ---- ----- ------
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07 2 5 zp ........ RMB0 $12
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17 2 5 zp ........ RMB1 $12
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27 2 5 zp ........ RMB2 $12
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37 2 5 zp ........ RMB3 $12
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47 2 5 zp ........ RMB4 $12
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57 2 5 zp ........ RMB5 $12
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67 2 5 zp ........ RMB6 $12
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77 2 5 zp ........ RMB7 $12
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87 2 5 zp ........ SMB0 $12
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97 2 5 zp ........ SMB1 $12
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A7 2 5 zp ........ SMB2 $12
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B7 2 5 zp ........ SMB3 $12
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C7 2 5 zp ........ SMB4 $12
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D7 2 5 zp ........ SMB5 $12
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E7 2 5 zp ........ SMB6 $12
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F7 2 5 zp ........ SMB7 $12
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**/
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#ifndef DISASSEMBLER
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#define RMB(n) INSTR void RMB##n( uint8_t zpg ) { \
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dbgPrintf("RMB"#n" "); \
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disPrintf(disassembly.inst, "RMB"#n); \
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WRZEROPG[zpg] &= ~(1 << n); \
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}
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#else
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#define RMB(n) INSTR void RMB##n( uint8_t zpg ) { \
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dbgPrintf("RMB"#n" "); \
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disPrintf(disassembly.inst, "RMB"#n); \
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}
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#endif
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RMB(0)
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RMB(1)
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RMB(2)
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RMB(3)
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RMB(4)
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RMB(5)
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RMB(6)
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RMB(7)
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#ifndef DISASSEMBLER
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#define SMB(n) INSTR void SMB##n( uint8_t zpg ) { \
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dbgPrintf("SMB"#n" "); \
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disPrintf(disassembly.inst, "SMB"#n); \
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WRZEROPG[zpg] |= (1 << n); \
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}
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#else
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#define SMB(n) INSTR void SMB##n( uint8_t zpg ) { \
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dbgPrintf("SMB"#n" "); \
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disPrintf(disassembly.inst, "SMB"#n); \
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}
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#endif
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SMB(0)
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SMB(1)
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SMB(2)
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SMB(3)
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SMB(4)
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SMB(5)
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SMB(6)
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SMB(7)
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#endif // __6502_INSTR_SET_CLR_H__
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