mirror of
https://github.com/trudnai/Steve2.git
synced 2024-06-10 20:29:33 +00:00
fddb1d9642
- HiRes support - Reset Vector fixes - ROM read from file - Better MMIO Handling - BugFixes - Shader Metal try
570 lines
14 KiB
C
570 lines
14 KiB
C
//
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// main.c
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// 6502
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//
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// Created by Tamas Rudnai on 7/14/19.
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// Copyright © 2019 GameAlloy. All rights reserved.
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//
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#ifndef __APPLE2_MMIO_H__
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#define __APPLE2_MMIO_H__
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#include "common.h"
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#include "6502.h"
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uint8_t Apple2_64K_RAM[ 64 * KB ] = {0};
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uint8_t * RAM = Apple2_64K_RAM;
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enum slot {
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SLOT0 = 0x00,
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SLOT1 = 0x10,
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SLOT2 = 0x20,
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SLOT3 = 0x30,
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SLOT4 = 0x40,
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SLOT5 = 0x50,
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SLOT6 = 0x60,
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SLOT7 = 0x70,
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};
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enum mmio {
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io_KBD = 0xC000,
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io_KBDSTRB = 0xC010,
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io_DISK_PHASE0_OFF = 0xC080,
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io_DISK_PHASE0_ON = 0xC081,
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io_DISK_PHASE1_OFF = 0xC082,
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io_DISK_PHASE1_ON = 0xC083,
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io_DISK_PHASE2_OFF = 0xC084,
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io_DISK_PHASE2_ON = 0xC085,
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io_DISK_PHASE3_OFF = 0xC086,
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io_DISK_PHASE3_ON = 0xC087,
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io_DISK_POWER_OFF = 0xC088,
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io_DISK_POWER_ON = 0xC089,
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io_DISK_SELECT_1 = 0xC08A,
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io_DISK_SELECT_2 = 0xC08B,
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io_DISK_READ = 0xC08C,
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io_DISK_WRITE = 0xC08D,
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io_DISK_CLEAR = 0xC08E,
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io_DISK_SHIFT = 0xC08F,
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};
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#define PAGESIZE 256
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#define PAGES 16
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//uint8_t ram_0[PAGESIZE];
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//uint8_t ram_1[PAGESIZE];
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//uint8_t ram_2[PAGESIZE];
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//uint8_t ram_3[PAGESIZE];
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//uint8_t ram_4[PAGESIZE];
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//uint8_t ram_5[PAGESIZE];
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//uint8_t ram_6[PAGESIZE];
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//uint8_t ram_7[PAGESIZE];
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//uint8_t ram_8[PAGESIZE];
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//uint8_t ram_9[PAGESIZE];
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//uint8_t ram_A[PAGESIZE];
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//uint8_t ram_B[PAGESIZE];
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//uint8_t aui_C[PAGESIZE];
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//uint8_t rom_D[PAGESIZE];
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//uint8_t rom_E[PAGESIZE];
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//uint8_t rom_F[PAGESIZE];
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//
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//uint8_t * ram[PAGES] = {
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// ram_0,
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// ram_1,
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// ram_2,
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// ram_3,
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// ram_4,
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// ram_5,
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// ram_6,
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// ram_7,
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// ram_8,
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// ram_9,
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// ram_A,
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// ram_B,
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// aui_C,
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// rom_D,
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// rom_E,
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// rom_F,
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//};
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//uint8_t ( * mmio_read [ 64 * KB ] )( uint16_t addr );
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typedef union address16_u {
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uint16_t addr;
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struct {
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uint8_t offs;
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uint8_t page;
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};
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} address16_t;
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#define CASE_DISKII(x) \
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case io_DISK_PHASE0_OFF + SLOT##x: \
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printf("io_DISK_PHASE0_OFF (S%u)\n", x); \
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return 0; \
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case io_DISK_PHASE0_ON + SLOT##x: \
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printf("io_DISK_PHASE0_ON (S%u)\n", x); \
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return 0; \
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case io_DISK_PHASE1_OFF + SLOT##x: \
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printf("io_DISK_PHASE1_OFF (S%u)\n", x); \
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return 0; \
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case io_DISK_PHASE1_ON + SLOT##x: \
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printf("io_DISK_PHASE1_ON (S%u)\n", x); \
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return 0; \
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case io_DISK_PHASE2_OFF + SLOT##x: \
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printf("io_DISK_PHASE2_OFF (S%u)\n", x); \
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return 0; \
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case io_DISK_PHASE2_ON + SLOT##x: \
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printf("io_DISK_PHASE2_ON (S%u)\n", x); \
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return 0; \
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case io_DISK_PHASE3_OFF + SLOT##x: \
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printf("io_DISK_PHASE3_OFF (S%u)\n", x); \
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return 0; \
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case io_DISK_PHASE3_ON + SLOT##x: \
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printf("io_DISK_PHASE3_ON (S%u)\n", x); \
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return 0; \
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case io_DISK_POWER_OFF + SLOT##x: \
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printf("io_DISK_POWER_OFF (S%u)\n", x); \
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return 0; \
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case io_DISK_POWER_ON + SLOT##x: \
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printf("io_DISK_POWER_ON (S%u)\n", x); \
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return 0; \
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case io_DISK_SELECT_1 + SLOT##x: \
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printf("io_DISK_SELECT_1 (S%u)\n", x); \
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return 0; \
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case io_DISK_SELECT_2 + SLOT##x: \
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printf("io_DISK_SELECT_2 (S%u)\n", x); \
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return 0; \
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case io_DISK_READ + SLOT##x: \
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printf("io_DISK_READ (S%u)\n", x); \
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return 0; \
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case io_DISK_WRITE + SLOT##x: \
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printf("io_DISK_WRITE (S%u)\n", x); \
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return 0; \
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case io_DISK_CLEAR + SLOT##x: \
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printf("io_DISK_CLEAR (S%u)\n", x); \
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return 0; \
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case io_DISK_SHIFT + SLOT##x: \
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printf("io_DISK_SHIFT (S%u)\n", x); \
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return 0;
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static const minDiskPhaseNum = 0;
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static const maxDiskPhaseNum = 80;
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static int trackPhase = maxDiskPhaseNum;
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struct phase_t {
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uint8_t current : 2;
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uint8_t last : 2;
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} phase = {0};
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static const int8_t phaseTransition[4][4] = {
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{ 0, -1, 0, +1 },
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{ +1, 0, -1, 0 },
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{ 0, +1, 0, -1 },
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{ -1, 0, +1, 0 },
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};
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INLINE uint8_t ioRead( uint16_t addr ) {
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dbgPrintf("mmio read:%04X\n", addr);
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switch (addr) {
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case io_KBD:
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// if ( RAM[io_KBD] > 0x7F ) printf("io_KBD:%04X\n", addr);
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return RAM[io_KBD];
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case io_KBDSTRB:
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// TODO: This is very slow!
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// printf("io_KBDSTRB\n");
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return RAM[io_KBD] &= 0x7F;
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// CASE_DISKII(6)
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// TODO: Make code "card insertable to slot" / aka slot independent and dynamically add/remove
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case io_DISK_PHASE0_OFF + SLOT6:
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case io_DISK_PHASE1_OFF + SLOT6:
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case io_DISK_PHASE2_OFF + SLOT6:
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case io_DISK_PHASE3_OFF + SLOT6:
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dbgPrintf2("io_DISK_PHASE%u_OFF (S%u)\n", phase.current, 6);
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phase.last = phase.current;
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return 0;
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case io_DISK_PHASE0_ON + SLOT6:
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case io_DISK_PHASE1_ON + SLOT6:
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case io_DISK_PHASE2_ON + SLOT6:
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case io_DISK_PHASE3_ON + SLOT6: {
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phase.current = (addr - io_DISK_PHASE0_ON - SLOT6) / 2;
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trackPhase += phaseTransition[phase.current][phase.last];
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if ( trackPhase < minDiskPhaseNum ) {
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trackPhase = minDiskPhaseNum;
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}
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if ( trackPhase > maxDiskPhaseNum ) {
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trackPhase = maxDiskPhaseNum;
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}
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dbgPrintf2("io_DISK_PHASE%u_ON (S%u, trk:%u)\n", phase.current, 6, trackPhase);
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return 0;
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}
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case io_DISK_POWER_OFF + SLOT6:
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dbgPrintf2("io_DISK_POWER_OFF (S%u)\n", 6);
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return 0;
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case io_DISK_POWER_ON + SLOT6:
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dbgPrintf2("io_DISK_POWER_ON (S%u)\n", 6);
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return 0;
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case io_DISK_SELECT_1 + SLOT6:
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dbgPrintf2("io_DISK_SELECT_1 (S%u)\n", 6);
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return 0;
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case io_DISK_SELECT_2 + SLOT6:
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dbgPrintf2("io_DISK_SELECT_2 (S%u)\n", 6);
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return 0;
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case io_DISK_READ + SLOT6:
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dbgPrintf("io_DISK_READ (S%u)\n", 6);
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int track = woz_tmap.phase[trackPhase];
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if (trackOffset >= WOZ_TRACK_BYTE_COUNT ) {
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trackOffset = 0;
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}
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printf("offs:%u\n", trackOffset);
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return woz_trks[track].data[trackOffset++];
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case io_DISK_WRITE + SLOT6:
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dbgPrintf2("io_DISK_WRITE (S%u)\n", 6);
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return 0;
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case io_DISK_CLEAR + SLOT6:
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dbgPrintf2("io_DISK_CLEAR (S%u)\n", 6);
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return 0;
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case io_DISK_SHIFT + SLOT6:
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dbgPrintf2("io_DISK_SHIFT (S%u)\n", 6);
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return 0;
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default:
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return RAM[addr];
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}
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}
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void kbdInput ( uint8_t code ) {
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// printf("kbdInput: %02X ('%c')\n", code, isprint(code) ? code : ' ');
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switch ( code ) {
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// case '\n':
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// code = 0x0D;
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// break;
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//
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case 0x7F: // BackSlash
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code = 0x08;
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break;
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default:
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break;
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}
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code |= 0x80;
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while ( RAM[io_KBD] > 0x7F ) {
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usleep(10);
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}
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RAM[io_KBD] = code;
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}
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INLINE void ioWrite( uint16_t addr, uint8_t val ) {
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// printf("mmio:%04X\n", addr);
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switch (addr) {
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case io_KBD:
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return;
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default:
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break;
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}
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return;
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}
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/**
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Naive implementation of RAM read from address
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**/
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INLINE uint8_t memread_zp( uint8_t addr ) {
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return RAM[ addr ];
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}
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/**
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Naive implementation of RAM read from address
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**/
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INLINE uint8_t memread8( uint16_t addr ) {
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// if ( addr == 0xD2AD ) {
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// dbgPrintf("OUT OF MEMORY!\n");
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// }
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return RAM[ addr ];
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}
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/**
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Naive implementation of RAM read from address
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**/
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INLINE uint16_t memread16( uint16_t addr ) {
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return * (uint16_t*) (& RAM[ addr ]);
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}
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INLINE uint8_t memread( uint16_t addr ) {
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// switch ( ((address16_t)addr).page ) {
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// case 0xC0:
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// case 0xC1:
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// case 0xC2:
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// case 0xC3:
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// case 0xC4:
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// case 0xC5:
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// case 0xC6:
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// case 0xC7:
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// case 0xC8:
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// case 0xC9:
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// case 0xCA:
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// case 0xCB:
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// case 0xCC:
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// case 0xCD:
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// case 0xCE:
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// case 0xCF:
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// return ioRead(addr);
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//
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// defaut:
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// break;
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// }
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if ( (addr >= 0xC000) && (addr < 0xC0FF) ) {
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return ioRead(addr);
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}
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return memread8(addr);
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}
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/**
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Naive implementation of RAM read from address
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**/
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//INLINE uint16_t memioread16( uint16_t addr ) {
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// return (uint16_t)mmio_read[ addr ](addr);
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//}
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/**
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Naive implementation of RAM write to address
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**/
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static void memwrite_zp( uint8_t addr, uint8_t byte ) {
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RAM[ addr ] = byte;
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}
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/**
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Naive implementation of RAM write to address
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**/
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static void memwrite( uint16_t addr, uint8_t byte ) {
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// if ( addr >= 0xD000 ) {
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// // ROM
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// return;
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// }
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// if ( addr >= 0xC000 ) {
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// return mmioWrite(addr);
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// }
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//
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RAM[ addr ] = byte;
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}
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/**
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Fetching 1 byte from memory address pc (program counter)
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increase pc by one
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**/
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INLINE uint8_t fetch() {
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disHexB( disassembly.pOpcode, RAM[m6502.PC] );
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return memread( m6502.PC++ );
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}
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/**
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Fetching 2 bytes as a 16 bit number from memory address pc (program counter)
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increase pc by one
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**/
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INLINE uint16_t fetch16() {
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uint16_t word = memread16( m6502.PC );
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m6502.PC += 2;
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disHexW( disassembly.pOpcode, word );
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return word;
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}
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/**
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abs .... absolute OPC $LLHH,X
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operand is address; effective address is address incremented by X with carry **
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**/
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INLINE uint16_t addr_abs() {
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dbgPrintf("abs:%04X(%02X) ", *((uint16_t*)&RAM[m6502.PC]), RAM[*((uint16_t*)&RAM[m6502.PC])]);
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disPrintf(disassembly.oper, "$%04X", memread16(m6502.PC))
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return fetch16();
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}
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INLINE uint8_t src_abs() {
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return memread( addr_abs() );
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}
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INLINE uint8_t * dest_abs() {
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return & RAM[ addr_abs() ];
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}
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INLINE int8_t rel_addr() {
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disPrintf(disassembly.oper, "$%04X", m6502.PC + 1 + (int8_t)memread8(m6502.PC))
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return fetch();
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}
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INLINE uint16_t abs_addr() {
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disPrintf(disassembly.oper, "$%04X", memread16(m6502.PC))
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return fetch16();
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}
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INLINE uint16_t ind_addr() {
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disPrintf(disassembly.oper, "($%04X)", memread16(m6502.PC))
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return memread16( fetch16() );
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}
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/**
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abs,X .... absolute, X-indexed OPC $LLHH,X
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operand is address; effective address is address incremented by X with carry **
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**/
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INLINE uint16_t addr_abs_X() {
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dbgPrintf("abs,X:%04X(%02X) ", *((uint16_t*)&RAM[m6502.PC]) + m6502.X, RAM[*((uint16_t*)&RAM[m6502.PC]) + m6502.X]);
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disPrintf(disassembly.oper, "$%04X,X", memread16(m6502.PC))
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return fetch16() + m6502.X;
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}
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INLINE uint8_t src_abs_X() {
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return memread( addr_abs_X() );
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}
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INLINE uint8_t * dest_abs_X() {
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return & RAM[ addr_abs_X() ];
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}
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/**
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abs,Y .... absolute, Y-indexed OPC $LLHH,Y
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operand is address; effective address is address incremented by Y with carry **
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**/
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INLINE uint16_t addr_abs_Y() {
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dbgPrintf("abs,Y:%04X(%02X) ", *((uint16_t*)&RAM[m6502.PC]) + m6502.Y, RAM[*((uint16_t*)&RAM[m6502.PC]) + m6502.Y]);
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disPrintf(disassembly.oper, "$%04X,Y", memread16(m6502.PC))
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return fetch16() + m6502.Y;
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}
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INLINE uint8_t src_abs_Y() {
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return memread(addr_abs_Y());
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}
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INLINE uint8_t * dest_abs_Y() {
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return & RAM[ addr_abs_Y() ];
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}
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INLINE uint16_t imm() {
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disPrintf(disassembly.oper, "#$%02X", memread8(m6502.PC))
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return fetch();
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}
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/**
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zpg .... zeropage OPC $LL
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operand is zeropage address (hi-byte is zero, address = $00LL)
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**/
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INLINE uint8_t addr_zp() {
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dbgPrintf("zp:%02X(%02X) ", RAM[m6502.PC], RAM[ RAM[m6502.PC]] );
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disPrintf(disassembly.oper, "$%02X", memread8(m6502.PC))
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return fetch();
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}
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INLINE uint8_t src_zp() {
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return memread_zp(addr_zp());
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}
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INLINE uint8_t * dest_zp() {
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return & RAM[ addr_zp() ];
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}
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/**
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get a 16 bit address from the zp:zp+1
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**/
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INLINE uint16_t addr_zp_ind( uint8_t addr ) {
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dbgPrintf("zpi:%02X:%04X(%02X) ", RAM[m6502.PC], *((uint16_t*)&RAM[m6502.PC]), RAM[*((uint16_t*)&RAM[m6502.PC])]);
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disPrintf(disassembly.oper, "($%02X) {$%04X}", memread8(m6502.PC), memread16( memread8(m6502.PC) ) )
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return memread16(addr);
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}
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/**
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X,ind .... X-indexed, indirect OPC ($LL,X)
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operand is zeropage address;
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effective address is word in (LL + X, LL + X + 1), inc. without carry: C.w($00LL + X)
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**/
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INLINE uint16_t addr_X_ind() {
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dbgPrintf("zpXi:%02X:%04X(%02X) ", RAM[m6502.PC], *((uint16_t*)&RAM[m6502.PC]) + m6502.X, RAM[*((uint16_t*)&RAM[m6502.PC]) + m6502.X]);
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disPrintf(disassembly.oper, "($%02X,X) {$%04X}", memread8(m6502.PC), memread16( memread8(m6502.PC) + m6502.X) )
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return memread16( fetch() + m6502.X );
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}
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INLINE uint8_t src_X_ind() {
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return memread( addr_X_ind() );
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}
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INLINE uint8_t * dest_X_ind() {
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return & RAM[ addr_X_ind() ];
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}
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/**
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ind,Y .... indirect, Y-indexed OPC ($LL),Y
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operand is zeropage address;
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effective address is word in (LL, LL + 1) incremented by Y with carry: C.w($00LL) + Y
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**/
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INLINE uint16_t addr_ind_Y() {
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// uint8_t a = fetch();
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// dbgPrintf("addr_ind_Y: %04X + %02X = %04X ", addr_zpg_ind( a ), m6502.Y, addr_zpg_ind( a ) + m6502.Y);
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disPrintf(disassembly.oper, "($%02X),Y {$%04X}", memread8(m6502.PC), memread16( memread8(m6502.PC) ) + m6502.Y)
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|
return memread16( fetch() ) + m6502.Y;
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|
}
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INLINE uint8_t src_ind_Y() {
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|
return memread( addr_ind_Y() );
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|
}
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INLINE uint8_t * dest_ind_Y() {
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|
uint16_t addr = addr_ind_Y();
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// if ( (addr >= 0xC000) && (addr <= 0xC0FF) ) {
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|
// addr = 0xC111;
|
|
// }
|
|
// return & RAM[ addr_abs_Y() ];
|
|
return & RAM[ addr ];
|
|
// return & RAM[ addr_ind_Y() ];
|
|
}
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|
|
|
/**
|
|
zpg,X .... zeropage, X-indexed OPC $LL,X
|
|
operand is zeropage address;
|
|
effective address is address incremented by X without carry **
|
|
**/
|
|
INLINE uint8_t addr_zp_X() {
|
|
disPrintf(disassembly.oper, "$%02X,X", memread8(m6502.PC))
|
|
return fetch() + m6502.X;
|
|
}
|
|
INLINE uint8_t src_zp_X() {
|
|
return memread_zp(addr_zp_X());
|
|
}
|
|
INLINE uint8_t * dest_zp_X() {
|
|
return & RAM[ addr_zp_X() ];
|
|
}
|
|
|
|
/**
|
|
zpg,Y .... zeropage, Y-indexed OPC $LL,Y
|
|
operand is zeropage address;
|
|
effective address is address incremented by Y without carry **
|
|
**/
|
|
INLINE uint8_t addr_zp_Y() {
|
|
disPrintf(disassembly.oper, "$%02X,Y", memread8(m6502.PC))
|
|
return fetch() + m6502.Y;
|
|
}
|
|
INLINE uint8_t src_zp_Y() {
|
|
return memread_zp(addr_zp_Y());
|
|
}
|
|
INLINE uint8_t * dest_zp_Y() {
|
|
return & RAM[ addr_zp_Y() ];
|
|
}
|
|
|
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#endif // __APPLE2_MMIO_H__
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