mirror of https://github.com/dschmenk/VM02.git
491 lines
8.7 KiB
ArmAsm
Executable File
491 lines
8.7 KiB
ArmAsm
Executable File
;*
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;* UTHERNET CARD DEVICE DRIVER
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;*
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;
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; UTHER PROBE AND INIT CODE
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;
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.IF .DEFINED (UTHERSLOT7)
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UTHER_PROBE7:
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.SCOPE
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UTHERSLOT = 7
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SLOTIO = $70
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SLOTROM = $C700
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.ELSEIF .DEFINED (UTHERSLOT6)
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UTHER_PROBE6:
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.SCOPE
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UTHERSLOT = 6
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SLOTIO = $60
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SLOTROM = $C600
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.ELSEIF .DEFINED (UTHERSLOT5)
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UTHER_PROBE5:
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.SCOPE
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UTHERSLOT = 5
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SLOTIO = $50
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SLOTROM = $C500
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.ELSEIF .DEFINED (UTHERSLOT4)
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UTHER_PROBE4:
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.SCOPE
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UTHERSLOT = 4
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SLOTIO = $40
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SLOTROM = $C400
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.ELSEIF .DEFINED (UTHERSLOT2)
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UTHER_PROBE2:
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.SCOPE
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UTHERSLOT = 2
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SLOTIO = $20
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SLOTROM = $C200
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.ELSEIF .DEFINED (UTHERSLOT1)
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UTHER_PROBE1:
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.SCOPE
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UTHERSLOT = 1
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SLOTIO = $10
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SLOTROM = $C100
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.ENDIF
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SRCHUTHR: STA TMPTR
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@CHKSIG: LDA SLOTROM+$05 ; NO ROM SIG FOR UTHERNET
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CMP #$38
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BNE @CHKAUTOSTRT
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LDA SLOTROM+$07
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CMP #$18
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BNE @CHKAUTOSTRT
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JMP @SKIPUTHR
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@CHKAUTOSTRT: LDA SLOTROM+$01
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CMP #$20
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BNE @CHKGT ; MAKE SURE IT ISN'T AUTOSTART DEVICE
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LDA SLOTROM+$05
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CMP #$03
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BNE @CHKGT
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JMP @SKIPUTHR
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@CHKGT: LDA SLOTROM+$01 ; MAKE SURE IT ISN'T GRAPHICS TABLET
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CMP #$B0
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BNE @CHKUTHR
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LDA SLOTROM+$09
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CMP #$20
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BNE @CHKUTHR
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@SKIPUTHR: SEC
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RTS
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@CHKUTHR: LDA #$00 ; SET PACKET PAGE POINTER
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STA $C08A+SLOTIO
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STA $C08B+SLOTIO
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LDA $C08C+SLOTIO
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CMP #$0E ; LOOK FOR MAGIC VENDOR ID
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BNE @SKIPUTHR
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LDA $C08D+SLOTIO
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CMP #$63
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BNE @SKIPUTHR
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@UTHER_INIT: LDA #$00
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STA $07F8+UTHERSLOT ; CLEAR FLAGS
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LDA #$14 ; RESET CHIP
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STA $C08A+SLOTIO
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LDA #$01
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STA $C08B+SLOTIO
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LDA #$55
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STA $C08C+SLOTIO
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LDA #$00
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STA $C08D+SLOTIO
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CLC
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RTS
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.ENDSCOPE
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;
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; UTHER DRIVER CODE
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;
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.IF .DEFINED (UTHERSLOT7)
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UTHER_DRIVER7:
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.SCOPE
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UTHERSLOT = 7
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SLOTIO = $70
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.ELSEIF .DEFINED (UTHERSLOT6)
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UTHER_DRIVER6:
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.SCOPE
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UTHERSLOT = 6
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SLOTIO = $60
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.ELSEIF .DEFINED (UTHERSLOT5)
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UTHER_DRIVER5:
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.SCOPE
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UTHERSLOT = 5
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SLOTIO = $50
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.ELSEIF .DEFINED (UTHERSLOT4)
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UTHER_DRIVER4:
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.SCOPE
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UTHERSLOT = 4
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SLOTIO = $40
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.ELSEIF .DEFINED (UTHERSLOT2)
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UTHER_DRIVER2:
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.SCOPE
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UTHERSLOT = 2
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SLOTIO = $20
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.ELSEIF .DEFINED (UTHERSLOT1)
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UTHER_DRIVER1:
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.SCOPE
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UTHERSLOT = 1
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SLOTIO = $10
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.ENDIF
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@UTHER_DRVR_SZ: .WORD @UTHER_DRVR_END - @UTHER_DRVR_START
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@UTHER_READ_OFS: .WORD @UTHER_READ - @UTHER_DRVR_START
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@UTHER_WRITE_OFS: .WORD @UTHER_WRITE - @UTHER_DRVR_START
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@UTHER_CTRL_OFS: .WORD @UTHER_CTRL - @UTHER_DRVR_START
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@UTHER_IRQ_OFS: .WORD @UTHER_IRQ - @UTHER_DRVR_START
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@UTHER_DRVR_START:
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@UTHER_POLL: PHP ; CHECK FOR PENDING PACKET
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SEI
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LDA $07F8+UTHERSLOT ; CHECK NOT BUSY + ENABLE BITS
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BEQ :+ ; NOT ENABLED, CHECK KEYBOARD
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LSR
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BNE :+ ; BUSY, CHECK KEYBOARD
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LDA #$24
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STA $C08A+SLOTIO
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LDA #$01
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STA $C08B+SLOTIO
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LDA $C08D+SLOTIO
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LSR
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BCC :+
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LDA #$05
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STA $07F8+UTHERSLOT
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PLP
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JMP FAKE_IRQ ; HANDLE IT
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: PLP
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JMP KEYBD_POLL ; NO, POLL KEYBOARD
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@UTHER_READ: PHA ; READ DATA FROM PACKET MEMORY: BYTE COUNT IN AX
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LDA $0678+UTHERSLOT ; SET UP BUFFER POINTERS
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STA TMPTR
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LDA $06F8+UTHERSLOT
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STA TMPTR+1
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TXA
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TAY
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BEQ :+
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LDY #$00
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STA TMPTR+2
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@UTHRRDPAGES: LDA $C080+SLOTIO ; READ 256 BYTE PAGES
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STA (TMPTR),Y
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INY
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LDA $C081+SLOTIO
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STA (TMPTR),Y
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INY
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BNE @UTHRRDPAGES
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INC TMPTR+1
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DEC TMPTR+2
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BNE @UTHRRDPAGES
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: PLA
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LSR
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BEQ @UTHRRDBYTE
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STA TMPTR+2
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@UTHRRDSHORTS: LDA $C080+SLOTIO ; READ 16 BIT SHORTS
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STA (TMPTR),Y
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INY
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LDA $C081+SLOTIO
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STA (TMPTR),Y
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INY
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DEC TMPTR+2
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BNE @UTHRRDSHORTS
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@UTHRRDBYTE: BCC :+ ; CHECK FOR FINAL BYTE TO READ
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LDA $C080+SLOTIO
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STA (TMPTR),Y
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CLC
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: RTS
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@UTHER_WRITE: PHA ; WRITE DATA TO PACKET MEMORY: BYTECOUNT IN AX
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LDA $0578+UTHERSLOT ; SET UP BUFFER POINTERS
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STA TMPTR
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LDA $05F8+UTHERSLOT
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STA TMPTR+1
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TXA
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TAY
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BEQ :+
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LDY #$00
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STA TMPTR+2
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@UTHRWRPAGES: LDA (TMPTR),Y ; WRITE 256 BYTE PAGES
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STA $C080+SLOTIO
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INY
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LDA (TMPTR),Y
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STA $C081+SLOTIO
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INY
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BNE @UTHRWRPAGES
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INC TMPTR+1
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DEC TMPTR+2
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BNE @UTHRWRPAGES
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: PLA
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LSR
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BEQ @UTHRWRBYTE
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STA TMPTR+2
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@UTHRWRSHORTS: LDA (TMPTR),Y ; WRITE 16 BIT SHORTS
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STA $C080+SLOTIO
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INY
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LDA (TMPTR),Y
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STA $C081+SLOTIO
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INY
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DEC TMPTR+2
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BNE @UTHRWRSHORTS
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@UTHRWRBYTE: BCC :+ ; CHECK FOR FINAL BYTE TO WRITE
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LDA (TMPTR),Y
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STA $C080+SLOTIO
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CLC
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: RTS
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@UTHER_CTRL: PHA
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TYA ; GET IOCTL ENCODED WITH SLOT #
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AND #$F8 ; MASK OFF SLOT
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CMP #IOCTL_INBUFF
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BNE :+
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TXA
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STA $06F8+UTHERSLOT
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PLA
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STA $0678+UTHERSLOT
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CLC
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RTS
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: CMP #IOCTL_OUTBUFF
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BNE :+
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TXA
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STA $05F8+UTHERSLOT
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PLA
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STA $0578+UTHERSLOT
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CLC
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RTS
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: CMP #ETHRCTL_RECVPKT
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BNE :+
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SEI
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LDA $07F8+UTHERSLOT ; CHECK FLAGS
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BEQ @UTHRBADSTATE ; NOT ENABLED
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LSR
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; BCC UTHRBADSTATE ; NOT ENABLED
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LSR
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BCS @UTHRRCVWAIT ; BUSY, WAIT
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LSR
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BCS @UTHRRCVLEN ; PENDING PACKET
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LDA #$24 ; SET POINTER TO RECEIVE STATUS
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STA $C08A+SLOTIO
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LDA #$01
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STA $C08B+SLOTIO
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LDA $C08D+SLOTIO
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LSR
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BCS @UTHRRCVNOW ; PACKET ALREADY WAITING
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@UTHRRCVWAIT: CLI
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LDY CURRENT_THREAD
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JSR THREAD_NOTIMEOUT
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LDY #UTHERSLOT
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JSR THREAD_WAITIO
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SEI
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LDA $07F8+UTHERSLOT ; CHECK FLAGS
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CMP #$05
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BEQ @UTHRRCVLEN
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BNE @UTHRBADSTATE
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@UTHRRCVNOW: LDA SLOT2MASK+UTHERSLOT ; CLEAR ANY PENDING IRQ NOTIFIES
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EOR #$FF
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AND IO_NOTIFY ; HAS THIS SLOT NOTIFIED?
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STA IO_NOTIFY
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@UTHRRCVLEN: PLA ; DISCARD SAVED ACCUM
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LDA #$03 ; SET BUSY FLAG
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STA $07F8+UTHERSLOT
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LDA $C081+SLOTIO ; SKIP STATUS
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LDA $C080+SLOTIO
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LDX $C081+SLOTIO ; RETURN PACKET LENGTH
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LDA $C080+SLOTIO
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CLC
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RTS
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.IFDEF DEBUG
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@UTHRBADSTATE: JSR PUTSLN
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.ASCIIZ "BAD UTHERNET STATE"
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JMP THROW_INTERNALERR
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.ELSE
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@UTHRBADSTATE: PLA
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LDA #$00
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TAX
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SEC
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RTS
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.ENDIF
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: CMP #ETHRCTL_XMITPKT
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BNE :+
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SEI
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LDA $07F8+UTHERSLOT
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CMP #$01
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BNE @UTHRBADSTATE ; NOT ENABLED OR BUSY
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LDA #$03
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STA $07F8+UTHERSLOT ; SET BUSY FLAG
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@UTHRXMTCMD: STX TMP
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LDA #$C9
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STA $C084+SLOTIO
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LDA #$00
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STA $C085+SLOTIO
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PLA
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STA $C086+SLOTIO
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LDA TMP
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STA $C087+SLOTIO
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@UTHRXMTRETRY: LDA #$38 ; SET POINTER TO BUS STATUS
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STA $C08A+SLOTIO
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LDA #$01
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STA $C08B+SLOTIO
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LDA $C08D+SLOTIO
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LSR
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BCC @UTHRXMTNOTRDY
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CLC
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RTS
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@UTHRXMTNOTRDY: TXA
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CLI
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PHA
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.IFDEF DEBUG
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JSR KEYBD_POLL
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.ELSE
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JSR THREAD_YIELD
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.ENDIF
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PLA
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SEI
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TAX
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BNE @UTHRXMTRETRY ; ALWAYS TAKEN
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: CMP #ETHRCTL_DONEPKT
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BNE :+
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.IFDEF DEBUG
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LDA $07F8+UTHERSLOT ; CHECK FLAGS
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CMP #$03
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BNE @UTHRBADSTATE ; NOT ENABLED
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.ENDIF
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PLA
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SEI
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LDA #$24 ; SET POINTER TO RECEIVE STATUS
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STA $C08A+SLOTIO
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LDA #$01
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STA $C08B+SLOTIO
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LDA $C08D+SLOTIO
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ASL
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ASL
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ORA #$01 ; CLEAR BUSY AND UPDATE PENDING FLAGS
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STA $07F8+UTHERSLOT
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LSR
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BNE @UTHRDONENOTIFY ; NOTIFY IF PENDING PACKET
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RTS
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@UTHRDONENOTIFY: LDY #UTHERSLOT
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JMP THREAD_NOTIFYIO
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: CMP #ETHRCTL_SETMAC01
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BNE :+
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STX TMP
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LDA #$58 ; SET POINTER TO MAC 0/1
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STA $C08A+SLOTIO
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LDA #$01
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STA $C08B+SLOTIO
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PLA
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STA $C08C+SLOTIO
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LDA TMP
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STA $C08D+SLOTIO
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CLC
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RTS
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: CMP #ETHRCTL_SETMAC23
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BNE :+
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STX TMP
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LDA #$5A ; SET POINTER TO MAC 2/3
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STA $C08A+SLOTIO
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LDA #$01
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STA $C08B+SLOTIO
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PLA
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STA $C08C+SLOTIO
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LDA TMP
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STA $C08D+SLOTIO
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CLC
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RTS
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: CMP #ETHRCTL_SETMAC45
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BNE :+
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LDA #$5C ; SET POINTER TO MAC 4/5
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STA $C08A+SLOTIO
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LDA #$01
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STA $C08B+SLOTIO
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PLA
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STA $C08C+SLOTIO
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LDA TMP
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STA $C08D+SLOTIO
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CLC
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RTS
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: CMP #IOCTL_OPEN
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BNE :+
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PLA
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LDA #$04 ; ONLY RECEIVE VALID PACKETS
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STA $C08A+SLOTIO
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LDA #$01
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STA $C08B+SLOTIO
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LDA #$05
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STA $C08C+SLOTIO
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LDA #$0D
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STA $C08D+SLOTIO
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LDA #$12 ; ENABLE RX, TX
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STA $C08A+SLOTIO
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LDA #$01
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STA $C08B+SLOTIO
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LDA #$D3
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STA $C08C+SLOTIO
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LDA #$00
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STA $C08D+SLOTIO
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; LDA #$02 ; ENABLE IRQ
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; STA $C08A,X ; IRQ ISN'T CONNECTED BUT MAKES IT
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; LDA #$01 ; EASIER TO POLL FOR RECEIVED PACKETS
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; STA $C08B,X
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; LDA #$03
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; STA $C08C,X
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; LDA #$01
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; STA $C08D,X
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; LDA #$16
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; STA $C08A,X
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; LDA #$01
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; STA $C08B,X
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; LDA #$17
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; STA $C08C,X
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; LDA #$80
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; STA $C08D,X
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LDA #$01 ; SET ENABLE FLAG
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STA $07F8+UTHERSLOT
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CLC
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RTS
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: CMP #IOCTL_CLOSE
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BNE :+
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LDA #IOCTL_DEACTIVATE
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: CMP #IOCTL_DEACTIVATE
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BNE :+
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PLA
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LDA #$12 ; DISABLE RX, TX, AND IRQ
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STA $C08A+SLOTIO
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LDA #$01
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STA $C08B+SLOTIO
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LDA #$00
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STA $C08C+SLOTIO
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LDA #$00
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STA $C08D+SLOTIO
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LDA #$16
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STA $C08A+SLOTIO
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LDA #$01
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STA $C08B+SLOTIO
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LDA #$17
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STA $C08C+SLOTIO
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LDA #$00
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STA $C08D+SLOTIO
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LDA #$00 ; CLEAR FLAGS
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STA $07F8+UTHERSLOT
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LDY #UTHERSLOT
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JSR THREAD_NOTIFYIO ; WAKE UP ANY WAITING THREADS
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CLC
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RTS
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: CMP #IOCTL_ID
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BEQ :+
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PLA
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SEC
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RTS
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: PLA
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LDA #$E1 ; UTHER ID
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CLC
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RTS
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@UTHER_IRQ: LDA $07F8+UTHERSLOT
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BNE :+ ; SKIP IF NOT ENABLED
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@UTHRNOSERV: SEC
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RTS
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: CMP #$05 ; CHECK PENDING FLAG
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BNE :+
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CLC
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RTS
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: CMP #$01 ; CHECK ENABLED FLAG
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BNE @UTHRNOSERV ; BUSY, DON'T SERVICE YET
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LDA #$24 ; SET POINTER TO RECEIVE STATUS
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STA $C08A+SLOTIO
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LDA #$01
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STA $C08B+SLOTIO
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LDA $C08D+SLOTIO
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LSR
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BCC @UTHRNOSERV
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LDA #$05 ; SET BUSY AND PENDING FLAG
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STA $07F8+UTHERSLOT
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CLC
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RTS
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@UTHER_DRVR_END EQU *
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.ENDSCOPE |