mirror of
https://github.com/freewilll/apple2-go.git
synced 2024-09-27 17:55:56 +00:00
110 lines
4.9 KiB
Go
110 lines
4.9 KiB
Go
package main
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import (
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"testing"
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"github.com/freewilll/apple2/cpu"
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"github.com/freewilll/apple2/keyboard"
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"github.com/freewilll/apple2/mmu"
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"github.com/freewilll/apple2/system"
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"github.com/freewilll/apple2/video"
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"github.com/stretchr/testify/assert"
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)
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func TestBankSwitching(t *testing.T) {
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cpu.InitInstructionDecoder()
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mmu.InitRAM()
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mmu.InitApple2eROM()
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mmu.InitIO()
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cpu.Init()
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keyboard.Init()
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video.Init()
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system.Init()
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cpu.SetColdStartReset()
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cpu.Reset()
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// Sanity test that what we expect from the apple //e ROM is correct
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assert.Equal(t, uint8(0x6f), mmu.ReadMemory(0xd000)) // read from ROM
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assert.Equal(t, uint8(0xc3), mmu.ReadMemory(0xffff)) // read from ROM
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// Verify ROM & RAM settings at startup
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mmu.WipeRAM()
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assert.Equal(t, uint8(0xc3), mmu.ReadMemory(0xffff)) // read from ROM
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mmu.WriteMemory(0xffff, 0xff) // write to $ffff
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assert.Equal(t, uint8(0xc3), mmu.ReadMemory(0xffff)) // ROM value is the same
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assert.Equal(t, uint8(0xff), mmu.PhysicalMemory.MainMemory[0xffff]) // RAM has been updated
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mmu.WriteMemory(0xd000, 0xfe) // write to $d000
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assert.Equal(t, uint8(0x00), mmu.PhysicalMemory.MainMemory[0xc000]) // bank #1 RAM
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assert.Equal(t, uint8(0xfe), mmu.PhysicalMemory.MainMemory[0xd000]) // bank #2 RAM
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// Switch bank to 1, write and check physical memory
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mmu.SetD000Bank(1)
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mmu.SetUpperReadMappedToROM(false)
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mmu.WriteMemory(0xd000, 0xfd) // write to $d000
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assert.Equal(t, uint8(0xfd), mmu.PhysicalMemory.MainMemory[0xc000]) // bank #1 RAM
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assert.Equal(t, uint8(0xfe), mmu.PhysicalMemory.MainMemory[0xd000]) // bank #2 RAM
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// Enable RAM area for reading and check values
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mmu.SetUpperReadMappedToROM(false)
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assert.Equal(t, uint8(0xfd), mmu.ReadMemory(0xd000)) // read from bank #1 RAM
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mmu.SetD000Bank(2)
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assert.Equal(t, uint8(0xfe), mmu.ReadMemory(0xd000)) // read from bank #1 RAM
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// Enable ROM area for reading and check values
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mmu.SetUpperReadMappedToROM(true)
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assert.Equal(t, uint8(0x6f), mmu.ReadMemory(0xd000)) // read from ROM
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assert.Equal(t, uint8(0xc3), mmu.ReadMemory(0xffff)) // read from ROM
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// Set d000 RAM to bank 1, RAM to read only and attempt writes
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mmu.SetD000Bank(1)
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mmu.SetUpperRamReadOnly(true)
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assert.Equal(t, uint8(0xfd), mmu.PhysicalMemory.MainMemory[0xc000]) // bank #1 RAM
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assert.Equal(t, uint8(0xfe), mmu.PhysicalMemory.MainMemory[0xd000]) // bank #2 RAM
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mmu.WriteMemory(0xd000, 0x01) // attempt to write to read only RAM
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mmu.WriteMemory(0xffff, 0x02) // attempt to write to read only RAM
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assert.Equal(t, uint8(0xfd), mmu.PhysicalMemory.MainMemory[0xc000]) // bank #1 RAM is unchanged
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assert.Equal(t, uint8(0xfe), mmu.PhysicalMemory.MainMemory[0xd000]) // bank #2 RAM is unchanged
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assert.Equal(t, uint8(0xff), mmu.PhysicalMemory.MainMemory[0xffff]) // top of RAM is unchanged
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// Set RAM to write and write to it
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mmu.SetUpperRamReadOnly(false)
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mmu.WriteMemory(0xd000, 0xfc) // write to RAM
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mmu.WriteMemory(0xffff, 0xfb) // write to RAM
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assert.Equal(t, uint8(0xfc), mmu.PhysicalMemory.MainMemory[0xc000]) // bank #1 RAM has been updated
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assert.Equal(t, uint8(0xfe), mmu.PhysicalMemory.MainMemory[0xd000]) // bank #2 RAM is untouched
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assert.Equal(t, uint8(0xfb), mmu.PhysicalMemory.MainMemory[0xffff]) // top of RAM has been updated
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// Enable ROM area for reading and check values
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mmu.SetUpperReadMappedToROM(true)
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assert.Equal(t, uint8(0x6f), mmu.ReadMemory(0xd000)) // read from ROM
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assert.Equal(t, uint8(0xc3), mmu.ReadMemory(0xffff)) // read from ROM
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testSwitches(t)
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}
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func assertMemoryConfiguration(t *testing.T, address uint16, upperRamReadOnly bool, upperReadMappedToROM bool, d000Bank int) {
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mmu.WriteMemory(address, 0x00)
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// assert.Equal(t, upperRamReadOnly, mmu.UpperRamReadOnly)
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assert.Equal(t, upperReadMappedToROM, mmu.UpperReadMappedToROM)
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assert.Equal(t, d000Bank, mmu.D000Bank)
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}
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func testSwitches(t *testing.T) {
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assertMemoryConfiguration(t, 0xc080, true, false, 2)
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assertMemoryConfiguration(t, 0xc081, false, true, 2)
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assertMemoryConfiguration(t, 0xc082, true, true, 2)
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assertMemoryConfiguration(t, 0xc083, false, false, 2)
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assertMemoryConfiguration(t, 0xc084, true, false, 2)
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assertMemoryConfiguration(t, 0xc085, false, true, 2)
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assertMemoryConfiguration(t, 0xc086, true, true, 2)
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assertMemoryConfiguration(t, 0xc087, false, false, 2)
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assertMemoryConfiguration(t, 0xc088, true, false, 1)
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assertMemoryConfiguration(t, 0xc089, false, true, 1)
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assertMemoryConfiguration(t, 0xc08a, true, true, 1)
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assertMemoryConfiguration(t, 0xc08b, false, false, 1)
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assertMemoryConfiguration(t, 0xc08c, true, false, 1)
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assertMemoryConfiguration(t, 0xc08d, false, true, 1)
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assertMemoryConfiguration(t, 0xc08e, true, true, 1)
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assertMemoryConfiguration(t, 0xc08f, false, false, 1)
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}
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