mirror of
https://github.com/freewilll/apple2-go.git
synced 2024-09-27 17:55:56 +00:00
67 lines
1.8 KiB
Go
67 lines
1.8 KiB
Go
package main
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import (
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"fmt"
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"testing"
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"github.com/freewilll/apple2/cpu"
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"github.com/freewilll/apple2/mmu"
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"github.com/freewilll/apple2/system"
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)
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func testBellCycles(delay int) {
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// Add some code to $800
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mmu.WriteMemory(0x800, 0xa9) // LDA #delay
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mmu.WriteMemory(0x801, uint8(delay)) //
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mmu.WriteMemory(0x802, 0x20) // JSR $fca8 BELL
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mmu.WriteMemory(0x803, 0xa8) //
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mmu.WriteMemory(0x804, 0xfc) //
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mmu.WriteMemory(0x805, 0x00) // BRK
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// Run the code until the BRK instruction and count the cycles
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system.FrameCycles = 0
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showInstructions := false
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breakAddress := uint16(0x805)
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exitAtBreak := false
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disableFirmwareWait := false
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cpu.State.PC = 0x800
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cpu.Run(showInstructions, &breakAddress, exitAtBreak, disableFirmwareWait, system.CpuFrequency*1000)
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// See http://apple2.org.za/gswv/a2zine/GS.WorldView/Resources/USEFUL.TABLES/WAIT.DELAY.CR.txt
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expectedCycles := (26 + 27*delay + 5*delay*delay) / 2
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gotCycles := int(system.FrameCycles - 2) // Exclude the cycles taken by the LDA
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fmt.Printf("Delay %3d ", delay)
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if gotCycles == expectedCycles {
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fmt.Println("OK")
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} else {
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fmt.Printf("Failed expected %6d, got %6d\n", expectedCycles, gotCycles)
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}
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}
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// TestBell tests the nunber of cycles in the system BELL loop for different
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// values of the accumulator. This test was mainly used to diagnose a bug
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// related to sound frequencies being incorrect due to invalid cycle
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// housekeeping in the CPU branch code.
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func TestBell(t *testing.T) {
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cpu.InitInstructionDecoder()
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mmu.InitRAM()
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mmu.InitApple2eROM()
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cpu.Init()
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system.Init()
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testBellCycles(1)
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testBellCycles(2)
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testBellCycles(3)
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testBellCycles(4)
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testBellCycles(12)
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testBellCycles(0x10)
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testBellCycles(0x20)
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testBellCycles(0x40)
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testBellCycles(0x80)
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testBellCycles(0xc0)
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testBellCycles(0xff)
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}
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