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54 lines
1.3 KiB
C
54 lines
1.3 KiB
C
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/* This file is auto-generated for a specific architecture ABI */
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#define CPU_IRQCHECK 0
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#define CPU65_TRACE_PROLOGUE 4
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#define CPU65_TRACE_ARG 8
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#define CPU65_TRACE_ARG1 12
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#define CPU65_TRACE_ARG2 16
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#define CPU65_TRACE_EPILOGUE 20
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#define CPU65_TRACE_IRQ 24
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#define DEBUG_ILLEGAL_BCD 28
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#define CPU65_VMEM_R 32
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#define CPU65_VMEM_W 36
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#define CPU65_FLAGS_ENCODE 40
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#define CPU65_FLAGS_DECODE 44
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#define CPU65__OPCODES 48
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#define CPU65__OPCYCLES 52
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#define BASE_RAMRD 56
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#define BASE_RAMWRT 60
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#define BASE_TEXTRD 64
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#define BASE_TEXTWRT 68
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#define BASE_HGRRD 72
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#define BASE_HGRWRT 76
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#define BASE_STACKZP 80
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#define BASE_D000_RD 84
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#define BASE_E000_RD 88
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#define BASE_D000_WRT 92
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#define BASE_E000_WRT 96
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#define BASE_C3ROM 100
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#define BASE_C4ROM 104
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#define BASE_C5ROM 108
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#define BASE_CXROM 112
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#define SOFTSWITCHES 116
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#define GC_CYCLES_TIMER_0 120
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#define GC_CYCLES_TIMER_1 124
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#define CPU65_CYCLES_TO_EXECUTE 128
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#define CPU65_CYCLE_COUNT 132
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#define IRQ_CHECK_TIMEOUT 136
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#define INTERRUPT_VECTOR 140
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#define RESET_VECTOR 142
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#define CPU65_PC 144
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#define CPU65_EA 146
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#define CPU65_A 148
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#define CPU65_F 149
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#define CPU65_X 150
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#define CPU65_Y 151
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#define CPU65_SP 152
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#define CPU65_D 153
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#define CPU65_RW 154
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#define CPU65_OPCODE 155
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#define CPU65_OPCYCLES 156
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#define CPU65__SIGNAL 157
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#define JOY_BUTTON0 158
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#define JOY_BUTTON1 159
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#define EMUL_REINITIALIZE 160
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