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https://github.com/mauiaaron/apple2.git
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Fix cycle counts in CPU tests after upheaval
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1294485a02
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@ -51,8 +51,10 @@ static void testcpu_setup(void *arg) {
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cpu65_uninterrupt(0xff);
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extern int32_t cpu65_cycles_to_execute;
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extern int32_t cpu65_cycle_count;
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extern int32_t irqCheckTimeout;
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cpu65_cycle_count = 0;
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cpu65_cycles_to_execute = 1;
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irqCheckTimeout = 255;
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cpu65_pc = TEST_LOC;
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cpu65_a = 0x0;
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@ -1798,9 +1800,10 @@ TEST test_BRK(void) {
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// FIXME TODO : this tests the Apple //e vm, so it prolly should be moved machine/memory tests ...
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TEST test_IRQ(void) {
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testcpu_set_opcode1(0xea/*NOP*/); // Implementation NOTE: first an instruction, then reset is handled
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testcpu_set_opcode1(0xea/*NOP*/); // Implementation NOTE: not executed. IRQ is handled and one BIT instruction at C3FA location is executed
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cpu65_interrupt(IRQGeneric);
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softswitches |= SS_C3ROM;
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ASSERT(apple_ii_64k[0][0x1ff] != 0x1f);
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ASSERT(apple_ii_64k[0][0x1fe] != TEST_LOC_LO+1);
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@ -1827,7 +1830,11 @@ TEST test_IRQ(void) {
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ASSERT(cpu65_d == 0xff);
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ASSERT(cpu65_rw == RW_READ);
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ASSERT(cpu65_opcode == 0x2c);
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ASSERT(cpu65_opcycles == (4));
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ASSERT(cpu65_opcycles == 11); // 4 cycles BIT instruction + 7 cycles for IRQ handling
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ASSERT(cpu65_cycle_count == 11);
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softswitches &= ~SS_C3ROM;
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cpu65_uninterrupt(IRQGeneric);
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PASS();
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}
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@ -2783,12 +2790,9 @@ TEST test_DEC_abs_x(uint8_t regA, uint8_t val, uint8_t regX, uint8_t lobyte, uin
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testcpu_set_opcode3(0xde, lobyte, hibyte);
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uint8_t cycle_count = 6;
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uint8_t cycle_count = 7;
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uint16_t addrs = lobyte | (hibyte<<8);
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addrs = addrs + regX;
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if ((uint8_t)((addrs>>8)&0xff) != (uint8_t)hibyte) {
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++cycle_count;
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}
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apple_ii_64k[0][addrs] = val;
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cpu65_a = regA;
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@ -3436,12 +3440,9 @@ TEST test_INC_abs_x(uint8_t regA, uint8_t val, uint8_t regX, uint8_t lobyte, uin
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testcpu_set_opcode3(0xfe, lobyte, hibyte);
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uint8_t cycle_count = 6;
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uint8_t cycle_count = 7;
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uint16_t addrs = lobyte | (hibyte<<8);
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addrs = addrs + regX;
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if ((uint8_t)((addrs>>8)&0xff) != (uint8_t)hibyte) {
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++cycle_count;
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}
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apple_ii_64k[0][addrs] = val;
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cpu65_a = regA;
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