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Streamline 65c02 cpu on ARM

This commit is contained in:
Aaron Culliney 2019-10-16 17:55:48 -07:00
parent 2615351d46
commit 1491d3f88d
5 changed files with 599 additions and 709 deletions
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24
src/arm/cpu-regs.h
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@ -22,13 +22,17 @@
// ARM register mappings
#define bz beq
#define bnz bne
#define bz beq
#define bnz bne
#define ROR_BIT 0x80000000
#define ROR_BIT 0x80000000
#define ROR_SHIFT 30
#ifdef __aarch64__
// NOTE: currently cpu.S contains unified ARM code that sacrifices using some 64bit scratch registers in favor of common codepath.
// We could further optimize the 64 bit port in the future if we separate it out ...
# define DOT_ARM
# define ALIGN .align 2;
# define PTR_SHIFT #3 // 1<<3 = 8
@ -42,8 +46,11 @@
# define wr0 w0 /* scratch/"important byte" */
# define xr1 x1 /* scratch */
# define wr1 w1 /* scratch */
# define wr9 w2 /* scratch */
# define wr9 w2
# define xr12 x5 /* overloaded both scratch */
# define wr12 w5 /* and also ... */
# define arm_flags x5 /* arm_flags (Flag_() macros) */
// NOTE: ARMv8 Procedure Call Standard indicates that x19-x28 are callee saved ... so we can call back into C without needing to
// first save these ...
@ -61,8 +68,6 @@
# define reg_args x26 /* cpu65_run() args register */
# define reg_vmem_r x27 /* cpu65_vmem_r table address */
# define xr12 x28 /* scratch */
# define wr12 w28 /* scratch */
// x29 : frame pointer (callee-saved)
// x30 : return address
// xzr/wzr : zero register
@ -83,9 +88,6 @@
# define xr1 r1 /* scratch */
# define wr1 r1 /* scratch */
# define wr9 r9 /* scratch */
// r12 is "ARM Intra-Procedure-call scratch register" ... used as a scratch register
# define xr12 r12 /* scratch */
# define wr12 r12 /* scratch */
// NOTE: these need to be preserved in subroutine (C) invocations ... */
# define EffectiveAddr r2 /* 16bit Effective address */
@ -105,6 +107,10 @@
// r9 is "ARM platform register" ... used as a scratch register
# define reg_args r10 /* cpu65_run() args register */
# define reg_vmem_r r11 /* cpu65_vmem_r table address */
// r12 is "ARM Intra-Procedure-call scratch register" ... used as a scratch register
# define xr12 r12 /* overloaded both scratch */
# define wr12 r12 /* and also ... */
# define arm_flags r12 /* arm_flags (Flag_() macros) */
// r13 ARM SP
// r14 ARM LR (return addr)
// r15 ARM PC

1274
src/arm/cpu.S
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File diff suppressed because it is too large Load Diff

6
src/cpu-supp.c
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@ -567,8 +567,8 @@ uint8_t cpu65__opcycles[256] = {
// NOTE: currently this is a conversion table between i386 flags <-> 6502 P register
static void init_flags_conversion_tables(void) {
for (unsigned i = 0; i < 256; i++) {
unsigned char val = 0;
for (unsigned int i = 0; i < 256; i++) {
uint8_t val = 0;
if (i & C_Flag) {
val |= C_Flag_6502;
@ -603,7 +603,7 @@ static void init_flags_conversion_tables(void) {
}
cpu65_flags_encode[ i ] = val;
cpu65_flags_decode[ val ] = i;
cpu65_flags_decode[ val ] = (uint8_t)i;
}
}

1
src/cpu.h
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@ -89,6 +89,7 @@ void cpu65_trace_checkpoint(void);
# define N_Flag 0x80 /* 6502 Negative */
#elif defined(__arm__) || defined(__aarch64__)
// VCZN positions match positions of shifted status register
// ALSO NOTE : changing these WILL AFFECT custom shifting in arm/cpu.S ...
# define V_Flag 0x1
# define C_Flag 0x2
# define Z_Flag 0x4

3
src/vm.c
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@ -1039,10 +1039,9 @@ GLUE_C_READ(iie_read_slot_expansion)
return apple_ii_64k[1][ea];
}
GLUE_C_READ(debug_illegal_bcd)
GLUE_C_WRITE(debug_illegal_bcd)
{
LOG("Illegal/undefined BCD operation encountered, debug break on c_debug_illegal_bcd to debug...");
return 0;
}
// ----------------------------------------------------------------------------