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https://github.com/mauiaaron/apple2.git
synced 2024-12-24 02:33:19 +00:00
test setting/checking ALTZP
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5d8fccefa9
commit
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@ -214,9 +214,19 @@ TEST test_read_random() {
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#define ASM_ALTZP_OFF() \
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test_type_input(" STA $C008\r")
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#define ASM_ALTZP_MAIN() ASM_ALTZP_OFF()
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#define ASM_ALTZP_ON() \
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test_type_input(" STA $C009\r")
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#define ASM_ALTZP_AUX() ASM_ALTZP_ON()
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#define ASM_CHECK_ALTZP() \
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test_type_input( \
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" LDA $C016\r" \
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" STA $1F43\r" \
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)
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#define TYPE_TEXT_OFF() \
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test_type_input("POKE49232,0:REM C050 TEXT OFF\r")
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@ -293,6 +303,27 @@ TEST test_read_random() {
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#define ASM_IIE_C08F() ASM_IIE_C08B()
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#define ASM_LCROM_BANK1() \
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test_type_input(" STA $C08A\r")
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#define ASM_LCRW_BANK1() \
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ASM_LCROM_BANK1(); \
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test_type_input( \
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" STA $C08B\r" \
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" STA $C08B\r" \
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)
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#define ASM_LCRD_BANK1() \
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ASM_LCROM_BANK1(); \
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test_type_input(" STA $C088\r");
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#define ASM_LCWRT_BANK1() \
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ASM_LCROM_BANK1(); \
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test_type_input( \
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" STA $C089\r" \
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" STA $C089\r" \
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)
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#define TYPE_TRIGGER_WATCHPT() \
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test_type_input("POKE7987,255:REM TRIGGER DEBUGGER\r")
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@ -1955,6 +1986,207 @@ TEST test_check_ramwrt(bool flag_ramwrt) {
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PASS();
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}
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TEST test_altzp_main(bool flag_lcram, bool flag_lcwrt) {
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BOOT_TO_DOS();
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ASSERT(apple_ii_64k[0][WATCHPOINT_ADDR] != TEST_FINISHED);
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ASM_INIT();
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ASM_ALTZP_AUX();
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ASM_LCROM_BANK1();
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if (flag_lcram) {
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if (flag_lcwrt) {
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ASM_LCRW_BANK1();
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} else {
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ASM_LCRD_BANK1();
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}
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} else if (flag_lcwrt) {
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ASM_LCWRT_BANK1();
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}
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ASM_TRIGGER_WATCHPT();
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ASM_ALTZP_MAIN();
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ASM_TRIGGER_WATCHPT();
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ASM_DONE();
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ASM_GO();
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c_debugger_go();
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ASSERT(apple_ii_64k[0][WATCHPOINT_ADDR] == TEST_FINISHED);
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ASSERT((softswitches & SS_ALTZP));
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ASSERT(flag_lcram ? (softswitches & SS_LCRAM) : !(softswitches & SS_LCRAM) );
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ASSERT(flag_lcwrt ? (softswitches & SS_LCWRT) : !(softswitches & SS_LCWRT) );
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ASSERT((base_stackzp == apple_ii_64k[1]));
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uint32_t switch_save = softswitches;
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uint8_t *save_base_d000_rd = base_d000_rd;
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uint8_t *save_base_d000_wrt = base_d000_wrt;
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uint8_t *save_base_e000_rd = base_e000_rd;
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uint8_t *save_base_e000_wrt = base_e000_wrt;
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int save_current_page = video__current_page;
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apple_ii_64k[0][WATCHPOINT_ADDR] = 0x00;
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c_debugger_go();
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ASSERT(apple_ii_64k[0][WATCHPOINT_ADDR] == TEST_FINISHED);
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ASSERT(!(softswitches & SS_ALTZP));
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ASSERT(flag_lcram ? (softswitches & SS_LCRAM) : !(softswitches & SS_LCRAM) );
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ASSERT(flag_lcwrt ? (softswitches & SS_LCWRT) : !(softswitches & SS_LCWRT) );
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ASSERT((base_stackzp == apple_ii_64k[0]));
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switch_save = switch_save & ~SS_ALTZP;
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if (flag_lcram) {
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ASSERT(base_d000_rd == save_base_d000_rd-0x2000);
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ASSERT(base_e000_rd == language_card[0]-0xE000);
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if (flag_lcwrt) {
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ASSERT(base_d000_wrt == save_base_d000_wrt-0x2000);
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ASSERT(base_e000_wrt == language_card[0]-0xE000);
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} else {
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ASSERT(base_d000_wrt == save_base_d000_wrt);
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ASSERT(base_e000_wrt == save_base_e000_wrt);
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}
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} else if (flag_lcwrt) {
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ASSERT(base_d000_rd == save_base_d000_rd);
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ASSERT(base_e000_rd == save_base_e000_rd);
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ASSERT(base_d000_wrt == save_base_d000_wrt-0x2000);
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ASSERT(base_e000_wrt == language_card[0]-0xE000);
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} else {
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ASSERT(base_d000_rd == save_base_d000_rd);
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ASSERT(base_d000_wrt == save_base_d000_wrt);
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ASSERT(base_e000_rd == save_base_e000_rd);
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ASSERT(base_e000_wrt == save_base_e000_wrt);
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}
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ASSERT(video__current_page == save_current_page);
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ASSERT((softswitches ^ switch_save) == 0);
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PASS();
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}
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TEST test_altzp_aux(bool flag_lcram, bool flag_lcwrt) {
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BOOT_TO_DOS();
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ASSERT(apple_ii_64k[0][WATCHPOINT_ADDR] != TEST_FINISHED);
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ASM_INIT();
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ASM_ALTZP_MAIN();
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ASM_LCROM_BANK1();
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if (flag_lcram) {
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if (flag_lcwrt) {
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ASM_LCRW_BANK1();
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} else {
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ASM_LCRD_BANK1();
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}
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} else if (flag_lcwrt) {
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ASM_LCWRT_BANK1();
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}
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ASM_TRIGGER_WATCHPT();
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ASM_ALTZP_AUX();
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ASM_TRIGGER_WATCHPT();
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ASM_DONE();
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ASM_GO();
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c_debugger_go();
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ASSERT(apple_ii_64k[0][WATCHPOINT_ADDR] == TEST_FINISHED);
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ASSERT(!(softswitches & SS_ALTZP));
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ASSERT(flag_lcram ? (softswitches & SS_LCRAM) : !(softswitches & SS_LCRAM) );
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ASSERT(flag_lcwrt ? (softswitches & SS_LCWRT) : !(softswitches & SS_LCWRT) );
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ASSERT((base_stackzp == apple_ii_64k[0]));
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uint32_t switch_save = softswitches;
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uint8_t *save_base_d000_rd = base_d000_rd;
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uint8_t *save_base_d000_wrt = base_d000_wrt;
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uint8_t *save_base_e000_rd = base_e000_rd;
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uint8_t *save_base_e000_wrt = base_e000_wrt;
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int save_current_page = video__current_page;
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apple_ii_64k[0][WATCHPOINT_ADDR] = 0x00;
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c_debugger_go();
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ASSERT(apple_ii_64k[0][WATCHPOINT_ADDR] == TEST_FINISHED);
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ASSERT((softswitches & SS_ALTZP));
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ASSERT(flag_lcram ? (softswitches & SS_LCRAM) : !(softswitches & SS_LCRAM) );
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ASSERT(flag_lcwrt ? (softswitches & SS_LCWRT) : !(softswitches & SS_LCWRT) );
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ASSERT((base_stackzp == apple_ii_64k[1]));
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switch_save = switch_save | SS_ALTZP;
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if (flag_lcram) {
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ASSERT(base_d000_rd == save_base_d000_rd+0x2000);
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ASSERT(base_e000_rd == language_card[0]-0xC000);
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if (flag_lcwrt) {
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ASSERT(base_d000_wrt == save_base_d000_wrt+0x2000);
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ASSERT(base_e000_wrt == language_card[0]-0xC000);
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} else {
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ASSERT(base_d000_wrt == save_base_d000_wrt);
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ASSERT(base_e000_wrt == save_base_e000_wrt);
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}
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} else if (flag_lcwrt) {
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ASSERT(base_d000_rd == save_base_d000_rd);
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ASSERT(base_e000_rd == save_base_e000_rd);
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ASSERT(base_d000_wrt == save_base_d000_wrt+0x2000);
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ASSERT(base_e000_wrt == language_card[0]-0xC000);
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} else {
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ASSERT(base_d000_rd == save_base_d000_rd);
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ASSERT(base_d000_wrt == save_base_d000_wrt);
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ASSERT(base_e000_rd == save_base_e000_rd);
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ASSERT(base_e000_wrt == save_base_e000_wrt);
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}
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ASSERT(video__current_page == save_current_page);
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ASSERT((softswitches ^ switch_save) == 0);
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PASS();
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}
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TEST test_check_altzp(bool flag_altzp) {
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BOOT_TO_DOS();
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ASSERT(apple_ii_64k[0][WATCHPOINT_ADDR] != TEST_FINISHED);
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ASM_INIT();
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if (flag_altzp) {
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ASM_ALTZP_ON();
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} else {
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ASSERT(!(softswitches & SS_ALTZP));
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}
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ASM_CHECK_ALTZP();
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ASM_TRIGGER_WATCHPT();
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ASM_DONE();
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ASM_GO();
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apple_ii_64k[0][TESTOUT_ADDR] = 0x96;
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c_debugger_go();
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ASSERT(apple_ii_64k[0][WATCHPOINT_ADDR] == TEST_FINISHED);
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if (flag_altzp) {
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ASSERT(apple_ii_64k[0][TESTOUT_ADDR] == 0x80);
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} else {
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ASSERT(apple_ii_64k[0][TESTOUT_ADDR] == 0x00);
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}
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PASS();
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}
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// ----------------------------------------------------------------------------
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// Test Suite
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@ -2081,6 +2313,19 @@ GREATEST_SUITE(test_suite_vm) {
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RUN_TESTp(test_check_ramwrt, /*RAMWRT*/0);
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RUN_TESTp(test_check_ramwrt, /*RAMWRT*/1);
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RUN_TESTp(test_altzp_main, /*LCRAM*/0, /*LCWRT*/0);
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RUN_TESTp(test_altzp_main, /*LCRAM*/0, /*LCWRT*/1);
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RUN_TESTp(test_altzp_main, /*LCRAM*/1, /*LCWRT*/0);
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RUN_TESTp(test_altzp_main, /*LCRAM*/1, /*LCWRT*/1);
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RUN_TESTp(test_altzp_aux, /*LCRAM*/0, /*LCWRT*/0);
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RUN_TESTp(test_altzp_aux, /*LCRAM*/0, /*LCWRT*/1);
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RUN_TESTp(test_altzp_aux, /*LCRAM*/1, /*LCWRT*/0);
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RUN_TESTp(test_altzp_aux, /*LCRAM*/1, /*LCWRT*/1);
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RUN_TESTp(test_check_altzp, /*ALTZP*/0);
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RUN_TESTp(test_check_altzp, /*ALTZP*/1);
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// ...
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c_eject_6(0);
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pthread_mutex_unlock(&interface_mutex);
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