mirror of
https://github.com/mauiaaron/apple2.git
synced 2024-06-26 00:29:27 +00:00
Varous VM switches return memory floating bus value
This commit is contained in:
Aaron Culliney
parent
381d97c485
commit
1ba28db8d7
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@ -23,6 +23,9 @@
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/* types */
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#define MEM_READ_FLAG (1<<0)
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#define MEM_WRITE_FLAG (1<<1)
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extern uint16_t cpu65_pc; // Program counter
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extern uint8_t cpu65_a; // Accumulator
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extern uint8_t cpu65_f; // Flags (host-order)
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@ -32,7 +35,7 @@ extern uint8_t cpu65_sp; // Stack Pointer
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extern uint16_t cpu65_ea; // Last effective address
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extern uint8_t cpu65_d; // Last data byte written
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extern uint8_t cpu65_rw; // 1 = read occured, 2 = write, 3 = both
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extern uint8_t cpu65_rw; // MEM_READ_FLAG = read occured, MEM_WRITE_FLAG = write
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extern uint8_t cpu65_opcode; // Last opcode
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extern uint8_t cpu65_opcycles; // Last opcode extra cycles
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14
src/misc.c
14
src/misc.c
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@ -262,12 +262,12 @@ void c_initialize_tables() {
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cpu65_vmem_r[0xC01E] = iie_check_altchar;
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/* SLOTC3ROM switch */
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cpu65_vmem_w[0xC00A] = iie_c3rom_internal; // HACK FIXME TODO VERIFY : the pattern here is reversed from cxrom?
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cpu65_vmem_w[0xC00A] = iie_c3rom_internal;
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cpu65_vmem_w[0xC00B] = iie_c3rom_peripheral;
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cpu65_vmem_r[0xC017] = iie_check_c3rom;
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/* SLOTCXROM switch */
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cpu65_vmem_w[0xC006] = iie_cxrom_peripheral; // HACK FIXME TODO VERIFY : the pattern here is reversed from c3rom?
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cpu65_vmem_w[0xC006] = iie_cxrom_peripheral;
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cpu65_vmem_w[0xC007] = iie_cxrom_internal;
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cpu65_vmem_r[0xC015] = iie_check_cxrom;
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@ -367,7 +367,7 @@ void c_initialize_tables() {
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/* Annunciator */
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for (i = 0xC058; i <= 0xC05D; i++) {
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cpu65_vmem_w[i] = cpu65_vmem_r[i] = iie_annunciator_noop;
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cpu65_vmem_w[i] = cpu65_vmem_r[i] = iie_annunciator;
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}
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/* DHIRES */
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@ -430,13 +430,9 @@ void c_initialize_tables() {
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for (i = 0xC800; i < 0xD000; i++)
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{
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cpu65_vmem_r[i] =
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iie_read_slot_expansion; /* expansion rom */
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cpu65_vmem_r[i] = iie_read_slot_expansion;
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}
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cpu65_vmem_r[0xCFFF] =
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cpu65_vmem_w[0xCFFF] =
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iie_disable_slot_expansion;
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cpu65_vmem_w[0xCFFF] = iie_read_slot_expansion;
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video_set(0);
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@ -192,7 +192,7 @@ iie_cxrom_peripheral(),
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iie_cxrom_internal(),
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iie_ioudis_on(),
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iie_ioudis_off(),
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iie_annunciator_noop(),
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iie_annunciator(),
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iie_dhires_on(),
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iie_dhires_off(),
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iie_hires_off(),
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@ -237,8 +237,8 @@ TEST test_boot_disk_cputrace() {
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}
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#endif
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#define EXPECTED_CPUTRACE_HELLO_DSK_FILE_SIZE 107523409
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#define EXPECTED_CPUTRACE_HELLO_DSK_SHA "586F218EC3C368C73DE1945B7EF441919E0D5B0F"
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#define EXPECTED_CPUTRACE_HELLO_FILE_SIZE 107500760
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#define EXPECTED_CPUTRACE_HELLO_SHA "CAF2507BAB937488F85377528041705114F06CA4"
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TEST test_cputrace_hello_dsk() {
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test_setup_boot_disk(BLANK_DSK, 0);
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@ -267,18 +267,18 @@ TEST test_cputrace_hello_dsk() {
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FILE *fp = fopen(output, "r");
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fseek(fp, 0, SEEK_END);
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long expectedSize = ftell(fp);
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ASSERT(expectedSize == EXPECTED_CPUTRACE_HELLO_DSK_FILE_SIZE);
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ASSERT(expectedSize == EXPECTED_CPUTRACE_HELLO_FILE_SIZE);
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fseek(fp, 0, SEEK_SET);
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unsigned char *buf = malloc(EXPECTED_CPUTRACE_HELLO_DSK_FILE_SIZE);
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if (fread(buf, 1, EXPECTED_CPUTRACE_HELLO_DSK_FILE_SIZE, fp) != EXPECTED_CPUTRACE_HELLO_DSK_FILE_SIZE) {
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unsigned char *buf = malloc(EXPECTED_CPUTRACE_HELLO_FILE_SIZE);
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if (fread(buf, 1, EXPECTED_CPUTRACE_HELLO_FILE_SIZE, fp) != EXPECTED_CPUTRACE_HELLO_FILE_SIZE) {
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ASSERT(false);
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}
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fclose(fp); fp = NULL;
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SHA1(buf, EXPECTED_CPUTRACE_HELLO_DSK_FILE_SIZE, md);
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SHA1(buf, EXPECTED_CPUTRACE_HELLO_FILE_SIZE, md);
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FREE(buf);
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sha1_to_str(md, mdstr0);
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ASSERT(strcmp(mdstr0, EXPECTED_CPUTRACE_HELLO_DSK_SHA) == 0);
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ASSERT(strcmp(mdstr0, EXPECTED_CPUTRACE_HELLO_SHA) == 0);
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} while(0);
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unlink(output);
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@ -287,8 +287,8 @@ TEST test_cputrace_hello_dsk() {
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PASS();
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}
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#define EXPECTED_CPUTRACE_HELLO_NIB_FILE_SIZE 12888005
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#define EXPECTED_CPUTRACE_HELLO_NIB_SHA "539A628524ACCF066A82FA67D0A488C8D3DC01BF"
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#define EXPECTED_CPUTRACE_HELLO_NIB_FILE_SIZE 12887880
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#define EXPECTED_CPUTRACE_HELLO_NIB_SHA "CE14642D70BA42B214C22BFB460F00AA54C8BB5C"
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TEST test_cputrace_hello_nib() {
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test_setup_boot_disk(BLANK_NIB, 0);
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@ -337,8 +337,6 @@ TEST test_cputrace_hello_nib() {
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PASS();
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}
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#define EXPECTED_CPUTRACE_HELLO_PO_FILE_SIZE 107523284
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#define EXPECTED_CPUTRACE_HELLO_PO_SHA "A99C1D02B898E02662DEDBF235C55B175D01D05D"
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TEST test_cputrace_hello_po() {
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test_setup_boot_disk(BLANK_PO, 0);
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@ -367,18 +365,18 @@ TEST test_cputrace_hello_po() {
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FILE *fp = fopen(output, "r");
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fseek(fp, 0, SEEK_END);
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long expectedSize = ftell(fp);
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ASSERT(expectedSize == EXPECTED_CPUTRACE_HELLO_PO_FILE_SIZE);
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ASSERT(expectedSize == EXPECTED_CPUTRACE_HELLO_FILE_SIZE);
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fseek(fp, 0, SEEK_SET);
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unsigned char *buf = malloc(EXPECTED_CPUTRACE_HELLO_PO_FILE_SIZE);
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if (fread(buf, 1, EXPECTED_CPUTRACE_HELLO_PO_FILE_SIZE, fp) != EXPECTED_CPUTRACE_HELLO_PO_FILE_SIZE) {
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unsigned char *buf = malloc(EXPECTED_CPUTRACE_HELLO_FILE_SIZE);
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if (fread(buf, 1, EXPECTED_CPUTRACE_HELLO_FILE_SIZE, fp) != EXPECTED_CPUTRACE_HELLO_FILE_SIZE) {
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ASSERT(false);
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}
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fclose(fp); fp = NULL;
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SHA1(buf, EXPECTED_CPUTRACE_HELLO_PO_FILE_SIZE, md);
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SHA1(buf, EXPECTED_CPUTRACE_HELLO_FILE_SIZE, md);
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FREE(buf);
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sha1_to_str(md, mdstr0);
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ASSERT(strcmp(mdstr0, EXPECTED_CPUTRACE_HELLO_PO_SHA) == 0);
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ASSERT(strcmp(mdstr0, EXPECTED_CPUTRACE_HELLO_SHA) == 0);
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} while(0);
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unlink(output);
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@ -387,8 +385,8 @@ TEST test_cputrace_hello_po() {
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PASS();
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}
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#define EXPECTED_VM_TRACE_FILE_SIZE 2830810
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#define EXPECTED_VM_TRACE_SHA "8B7A8169E34354773F82442DB6A0C3D6B69741D9"
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#define EXPECTED_VM_TRACE_FILE_SIZE 2830792
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#define EXPECTED_VM_TRACE_SHA "0659556B878848A6421D93057F18B3FB518A7D76"
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TEST test_boot_disk_vmtrace() {
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char *homedir = getenv("HOME");
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char *disk = NULL;
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@ -433,8 +431,8 @@ TEST test_boot_disk_vmtrace() {
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PASS();
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}
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#define EXPECTED_VM_TRACE_NIB_FILE_SIZE 2930074
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#define EXPECTED_VM_TRACE_NIB_SHA "BD2BA2B9C8E7712F9E6ABF1049ED8D2C4D979934"
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#define EXPECTED_VM_TRACE_NIB_FILE_SIZE 2930056
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#define EXPECTED_VM_TRACE_NIB_SHA "9C1B64255B1946011FAAF5DF53C24114401485EE"
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TEST test_boot_disk_vmtrace_nib() {
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test_setup_boot_disk(BLANK_NIB, 0);
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@ -481,8 +479,8 @@ TEST test_boot_disk_vmtrace_nib() {
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PASS();
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}
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#define EXPECTED_VM_TRACE_PO_FILE_SIZE 2830810
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#define EXPECTED_VM_TRACE_PO_SHA "3432149815E9142FDAD6D9DF94C8621FEB56F7D7"
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#define EXPECTED_VM_TRACE_PO_FILE_SIZE EXPECTED_VM_TRACE_FILE_SIZE
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#define EXPECTED_VM_TRACE_PO_SHA "23236C80A9CC38E75BB27F2E70359234B6B8D4DA"
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TEST test_boot_disk_vmtrace_po() {
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test_setup_boot_disk(BLANK_PO, 0);
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119
src/vm.c
119
src/vm.c
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@ -124,12 +124,12 @@ typedef struct vm_trace_range_t {
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GLUE_C_READ(ram_nop)
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{
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return 0x0;
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return (cpu65_rw&MEM_WRITE_FLAG) ? 0x0 : floating_bus(cpu65_cycle_count);
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}
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GLUE_C_READ(read_unmapped_softswitch)
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{
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return apple_ii_64k[0][ea];
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return c_ram_nop(ea);
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}
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GLUE_C_WRITE(write_unmapped_softswitch)
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@ -164,7 +164,7 @@ GLUE_C_READ(speaker_toggle)
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#ifdef AUDIO_ENABLED
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SpkrToggle();
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#endif
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return 0;
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return floating_bus(cpu65_cycle_count);
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}
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// ----------------------------------------------------------------------------
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@ -173,7 +173,7 @@ GLUE_C_READ(speaker_toggle)
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GLUE_C_READ(iie_page2_off)
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{
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if (!(softswitches & SS_PAGE2)) {
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return 0x0; // TODO: no early return?
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return floating_bus(cpu65_cycle_count);
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}
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softswitches &= ~(SS_PAGE2|SS_SCREEN);
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@ -191,13 +191,13 @@ GLUE_C_READ(iie_page2_off)
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video_setpage(0);
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return 0x0;
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return floating_bus(cpu65_cycle_count);
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}
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GLUE_C_READ(iie_page2_on)
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{
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if (softswitches & SS_PAGE2) {
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return 0x0; // TODO: no early return?
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return floating_bus(cpu65_cycle_count);
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}
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softswitches |= SS_PAGE2;
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@ -216,7 +216,7 @@ GLUE_C_READ(iie_page2_on)
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video_setpage(1);
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}
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return 0x0;
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return floating_bus(cpu65_cycle_count);
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}
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GLUE_C_READ(iie_check_page2)
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@ -230,7 +230,7 @@ GLUE_C_READ(read_switch_graphics)
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softswitches &= ~SS_TEXT;
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video_redraw();
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}
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return 0x0;
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return floating_bus(cpu65_cycle_count);
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}
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GLUE_C_READ(read_switch_text)
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@ -239,7 +239,7 @@ GLUE_C_READ(read_switch_text)
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softswitches |= SS_TEXT;
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video_redraw();
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}
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return 0x0;
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return floating_bus(cpu65_cycle_count);
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}
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GLUE_C_READ(iie_check_text)
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@ -253,7 +253,7 @@ GLUE_C_READ(read_switch_no_mixed)
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softswitches &= ~SS_MIXED;
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video_redraw();
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}
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return 0x0;
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return floating_bus(cpu65_cycle_count);
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}
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GLUE_C_READ(read_switch_mixed)
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@ -262,7 +262,7 @@ GLUE_C_READ(read_switch_mixed)
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softswitches |= SS_MIXED;
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video_redraw();
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}
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return 0x0;
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return floating_bus(cpu65_cycle_count);
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}
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GLUE_C_READ(iie_check_mixed)
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@ -270,15 +270,18 @@ GLUE_C_READ(iie_check_mixed)
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return (softswitches & SS_MIXED) ? 0x80 : 0x00;
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}
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GLUE_C_READ(iie_annunciator_noop)
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GLUE_C_READ(iie_annunciator)
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{
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return 0x0;// TBD : mem_floating_bus()
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if ((ea >= 0xC058) && (ea <= 0xC05B)) {
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// TODO: alternate joystick management?
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}
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return (cpu65_rw&MEM_WRITE_FLAG) ? 0x0 : floating_bus(cpu65_cycle_count);
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}
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GLUE_C_READ(iie_hires_off)
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{
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if (!(softswitches & SS_HIRES)) {
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return 0x0; // TODO: no early return?
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return floating_bus(cpu65_cycle_count);
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}
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softswitches &= ~(SS_HIRES|SS_HGRRD|SS_HGRWRT);
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@ -296,13 +299,13 @@ GLUE_C_READ(iie_hires_off)
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}
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video_redraw();
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return 0x0;
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return floating_bus(cpu65_cycle_count);
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}
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GLUE_C_READ(iie_hires_on)
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{
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if (softswitches & SS_HIRES) {
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return 0x0; // TODO: no early return?
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return floating_bus(cpu65_cycle_count);
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}
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softswitches |= SS_HIRES;
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@ -320,7 +323,7 @@ GLUE_C_READ(iie_hires_on)
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}
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video_redraw();
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return 0x0;
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return floating_bus(cpu65_cycle_count);
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}
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GLUE_C_READ(iie_check_hires)
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@ -366,7 +369,7 @@ GLUE_C_READ(read_gc_strobe)
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}
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// NOTE (possible TODO FIXME): unimplemented GC2 and GC3 timers since they were not wired on the //e ...
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return 0x0;
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return floating_bus(cpu65_cycle_count);
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}
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GLUE_C_READ(read_gc0)
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@ -391,12 +394,12 @@ GLUE_C_READ(read_gc1)
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GLUE_C_READ(iie_read_gc2)
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{
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return 0x0;
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return floating_bus(cpu65_cycle_count);
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}
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GLUE_C_READ(iie_read_gc3)
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{
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return 0x0;
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return floating_bus(cpu65_cycle_count);
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}
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// ----------------------------------------------------------------------------
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@ -428,7 +431,7 @@ GLUE_C_READ(iie_c080)
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if (softswitches & SS_ALTZP) {
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_lc_to_auxmem();
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}
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return 0x0;
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return floating_bus(cpu65_cycle_count);
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}
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GLUE_C_READ(iie_c081)
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@ -448,7 +451,7 @@ GLUE_C_READ(iie_c081)
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if (softswitches & SS_ALTZP) {
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_lc_to_auxmem();
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}
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return 0x0;
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return floating_bus(cpu65_cycle_count);
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}
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GLUE_C_READ(lc_c082)
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@ -462,7 +465,7 @@ GLUE_C_READ(lc_c082)
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base_d000_wrt = 0;
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base_e000_wrt = 0;
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return 0x0;
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return floating_bus(cpu65_cycle_count);
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}
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GLUE_C_READ(iie_c083)
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@ -480,7 +483,7 @@ GLUE_C_READ(iie_c083)
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if (softswitches & SS_ALTZP) {
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_lc_to_auxmem();
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}
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return 0x0;
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return floating_bus(cpu65_cycle_count);
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}
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GLUE_C_READ(iie_c088)
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@ -497,7 +500,7 @@ GLUE_C_READ(iie_c088)
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if (softswitches & SS_ALTZP) {
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_lc_to_auxmem();
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}
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return 0x0;
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return floating_bus(cpu65_cycle_count);
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}
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GLUE_C_READ(iie_c089)
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@ -517,7 +520,7 @@ GLUE_C_READ(iie_c089)
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if (softswitches & SS_ALTZP) {
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_lc_to_auxmem();
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}
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return 0x0;
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return floating_bus(cpu65_cycle_count);
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}
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GLUE_C_READ(lc_c08a)
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@ -530,7 +533,7 @@ GLUE_C_READ(lc_c08a)
|
|||
base_d000_wrt = 0;
|
||||
base_e000_wrt = 0;
|
||||
|
||||
return 0x0;
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
GLUE_C_READ(iie_c08b)
|
||||
|
|
@ -550,7 +553,7 @@ GLUE_C_READ(iie_c08b)
|
|||
if (softswitches & SS_ALTZP) {
|
||||
_lc_to_auxmem();
|
||||
}
|
||||
return 0x0;
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
GLUE_C_READ(iie_check_bank)
|
||||
|
|
@ -569,7 +572,7 @@ GLUE_C_READ(iie_check_lcram)
|
|||
GLUE_C_READ(iie_80store_off)
|
||||
{
|
||||
if (!(softswitches & SS_80STORE)) {
|
||||
return 0x0; // TODO: no early return?
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
softswitches &= ~(SS_80STORE|SS_TEXTRD|SS_TEXTWRT|SS_HGRRD|SS_HGRWRT);
|
||||
|
|
@ -596,13 +599,13 @@ GLUE_C_READ(iie_80store_off)
|
|||
video_setpage(1);
|
||||
}
|
||||
|
||||
return 0x0;
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
GLUE_C_READ(iie_80store_on)
|
||||
{
|
||||
if (softswitches & SS_80STORE) {
|
||||
return 0x0; // TODO: no early return?
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
softswitches |= SS_80STORE;
|
||||
|
|
@ -629,7 +632,7 @@ GLUE_C_READ(iie_80store_on)
|
|||
|
||||
softswitches &= ~SS_SCREEN;
|
||||
video_setpage(0);
|
||||
return 0x0;
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
GLUE_C_READ(iie_check_80store)
|
||||
|
|
@ -640,7 +643,7 @@ GLUE_C_READ(iie_check_80store)
|
|||
GLUE_C_READ(iie_ramrd_main)
|
||||
{
|
||||
if (!(softswitches & SS_RAMRD)) {
|
||||
return 0x0; // TODO: no early return?
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
softswitches &= ~SS_RAMRD;
|
||||
|
|
@ -657,13 +660,13 @@ GLUE_C_READ(iie_ramrd_main)
|
|||
base_hgrrd = apple_ii_64k[0];
|
||||
}
|
||||
|
||||
return 0x0;
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
GLUE_C_READ(iie_ramrd_aux)
|
||||
{
|
||||
if (softswitches & SS_RAMRD) {
|
||||
return 0x0; // TODO: no early return?
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
softswitches |= SS_RAMRD;
|
||||
|
|
@ -680,7 +683,7 @@ GLUE_C_READ(iie_ramrd_aux)
|
|||
base_hgrrd = apple_ii_64k[1];
|
||||
}
|
||||
|
||||
return 0x0;
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
GLUE_C_READ(iie_check_ramrd)
|
||||
|
|
@ -691,7 +694,7 @@ GLUE_C_READ(iie_check_ramrd)
|
|||
GLUE_C_READ(iie_ramwrt_main)
|
||||
{
|
||||
if (!(softswitches & SS_RAMWRT)) {
|
||||
return 0x0; // TODO: no early return?
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
softswitches &= ~SS_RAMWRT;
|
||||
|
|
@ -708,13 +711,13 @@ GLUE_C_READ(iie_ramwrt_main)
|
|||
base_hgrwrt = apple_ii_64k[0];
|
||||
}
|
||||
|
||||
return 0x0;
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
GLUE_C_READ(iie_ramwrt_aux)
|
||||
{
|
||||
if (softswitches & SS_RAMWRT) {
|
||||
return 0x0; // TODO: no early return?
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
softswitches |= SS_RAMWRT;
|
||||
|
|
@ -731,7 +734,7 @@ GLUE_C_READ(iie_ramwrt_aux)
|
|||
base_hgrwrt = apple_ii_64k[1];
|
||||
}
|
||||
|
||||
return 0x0;
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
GLUE_C_READ(iie_check_ramwrt)
|
||||
|
|
@ -743,7 +746,7 @@ GLUE_C_READ_ALTZP(iie_altzp_main)
|
|||
{
|
||||
if (!(softswitches & SS_ALTZP)) {
|
||||
/* NOTE : test if ALTZP already off - due to d000-bank issues it is *needed*, not just a shortcut */
|
||||
return 0x0;
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
softswitches &= ~SS_ALTZP;
|
||||
|
|
@ -759,14 +762,14 @@ GLUE_C_READ_ALTZP(iie_altzp_main)
|
|||
base_e000_wrt = language_card[0] - 0xE000;
|
||||
}
|
||||
|
||||
return 0x0;
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
GLUE_C_READ_ALTZP(iie_altzp_aux)
|
||||
{
|
||||
if (softswitches & SS_ALTZP) {
|
||||
/* NOTE : test if ALTZP already on - due to d000-bank issues it is *needed*, not just a shortcut */
|
||||
return 0x0;
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
softswitches |= SS_ALTZP;
|
||||
|
|
@ -774,7 +777,7 @@ GLUE_C_READ_ALTZP(iie_altzp_aux)
|
|||
|
||||
_lc_to_auxmem();
|
||||
|
||||
return 0x0;
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
GLUE_C_READ(iie_check_altzp)
|
||||
|
|
@ -785,7 +788,7 @@ GLUE_C_READ(iie_check_altzp)
|
|||
GLUE_C_READ(iie_80col_off)
|
||||
{
|
||||
if (!(softswitches & SS_80COL)) {
|
||||
return 0x0; // TODO: no early return?
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
softswitches &= ~SS_80COL;
|
||||
|
|
@ -794,13 +797,13 @@ GLUE_C_READ(iie_80col_off)
|
|||
video_redraw();
|
||||
}
|
||||
|
||||
return 0x0;
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
GLUE_C_READ(iie_80col_on)
|
||||
{
|
||||
if (softswitches & SS_80COL) {
|
||||
return 0x0;
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
softswitches |= SS_80COL;
|
||||
|
|
@ -809,7 +812,7 @@ GLUE_C_READ(iie_80col_on)
|
|||
video_redraw();
|
||||
}
|
||||
|
||||
return 0x0;
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
GLUE_C_READ(iie_check_80col)
|
||||
|
|
@ -823,7 +826,7 @@ GLUE_C_READ(iie_altchar_off)
|
|||
softswitches &= ~SS_ALTCHAR;
|
||||
c_set_primary_char();
|
||||
}
|
||||
return 0x0;
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
GLUE_C_READ(iie_altchar_on)
|
||||
|
|
@ -832,7 +835,7 @@ GLUE_C_READ(iie_altchar_on)
|
|||
softswitches |= SS_ALTCHAR;
|
||||
c_set_altchar();
|
||||
}
|
||||
return 0x0;
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
GLUE_C_READ(iie_check_altchar)
|
||||
|
|
@ -860,22 +863,20 @@ GLUE_C_READ(iie_check_ioudis)
|
|||
|
||||
GLUE_C_READ(iie_dhires_on)
|
||||
{
|
||||
// FIXME : does this depend on IOUDIS?
|
||||
if (!(softswitches & SS_DHIRES)) {
|
||||
softswitches |= SS_DHIRES;
|
||||
video_redraw();
|
||||
}
|
||||
return 0x0;
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
GLUE_C_READ(iie_dhires_off)
|
||||
{
|
||||
// FIXME : does this depend on IOUDIS?
|
||||
if (softswitches & SS_DHIRES) {
|
||||
softswitches &= ~SS_DHIRES;
|
||||
video_redraw();
|
||||
}
|
||||
return 0x0;
|
||||
return floating_bus(cpu65_cycle_count);
|
||||
}
|
||||
|
||||
GLUE_C_READ(iie_check_dhires)
|
||||
|
|
@ -949,16 +950,12 @@ GLUE_C_READ(iie_read_slot_expansion)
|
|||
{
|
||||
// HACK TODO FIXME : how does the expansion slot get referenced? Need to handle other ROMs that might use this area
|
||||
// ... Also Need moar tests ...
|
||||
if (ea == 0xCFFF) {
|
||||
// disable expansion ROM
|
||||
}
|
||||
return apple_ii_64k[1][ea];
|
||||
}
|
||||
|
||||
GLUE_C_READ(iie_disable_slot_expansion)
|
||||
{
|
||||
// HACK TODO FIXME : how does the expansion slot get referenced? Need to handle other ROMs that might use this area
|
||||
// ... Also Need moar tests ...
|
||||
return 0x0;
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
void debug_print_softwitches(void) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user