diff --git a/src/asm386/cpu.S b/src/asm386/cpu.S
index 14af6ba3..91c23ca5 100644
--- a/src/asm386/cpu.S
+++ b/src/asm386/cpu.S
@@ -2706,7 +2706,7 @@ continue:
                 subl    %eax, SN(gc_cycles_timer_1)
                 subw    %ax, SN(cpu65_cycles_to_execute)
                 jle     exit_cpu65_run
-                xorl    %eax, %eax
+continue1:      xorl    %eax, %eax
                 orb     SN(cpu65__signal), %al
                 jnz     exception
 1:              JumpNextInstruction
@@ -2760,7 +2760,7 @@ E(cpu65_run)
                 cmpb    $0, SN(emul_reinitialize)
                 jnz     1f
                 RestoreState
-                JumpNextInstruction
+                jmp     continue1
 1:              movb    $0, SN(emul_reinitialize)
                 /* Zero all registers, as well as the unused 32-bit parts
                  * of variables. (which may need to be kept 0)
diff --git a/src/test/testcpu.c b/src/test/testcpu.c
index 0ffffc5d..8f693409 100644
--- a/src/test/testcpu.c
+++ b/src/test/testcpu.c
@@ -47,7 +47,7 @@
 static void testcpu_setup(void *arg) {
 
     //reinitialize();
-
+    cpu65_uninterrupt(0xff);
     cpu65_cycles_to_execute = 1;
 
     cpu65_current.pc = TEST_LOC;
@@ -1755,7 +1755,6 @@ TEST test_IRQ() {
     // NOTE : not an opcode
     testcpu_set_opcode1(0xea/*NOP*/); // Implementation NOTE: first an instruction, then reset is handled
 
-    cpu65_cycles_to_execute = 3;
     cpu65_interrupt(IRQGeneric);
 
     ASSERT(apple_ii_64k[0][0x1ff] != 0x1f);
@@ -1776,7 +1775,7 @@ TEST test_IRQ() {
     ASSERT(cpu65_current.sp     == 0xfc);
 
     ASSERT(apple_ii_64k[0][0x1ff] == 0x1f);
-    ASSERT(apple_ii_64k[0][0x1fe] == TEST_LOC_LO+1);
+    ASSERT(apple_ii_64k[0][0x1fe] == TEST_LOC_LO);
     ASSERT(apple_ii_64k[0][0x1fd] == cpu65_flags_encode[X_Flag]);
 
     ASSERT(cpu65_debug.ea       == 0xc015);