mirror of
https://github.com/mauiaaron/apple2.git
synced 2025-01-12 06:29:58 +00:00
Get some CPU tests passing on ARM/Android
This commit is contained in:
Aaron Culliney
parent
43fa9c9357
commit
3149914741
@ -24,10 +24,10 @@
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#define Y_Reg r6 /* 8bit 6502 Y register */
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#define Y_Reg r6 /* 8bit 6502 Y register */
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#define X_Reg r7 /* 8bit 6502 X register */
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#define X_Reg r7 /* 8bit 6502 X register */
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#define A_Reg r8 /* 8bit 6502 A register */
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#define A_Reg r8 /* 8bit 6502 A register */
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// r9 is another scratch variable
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// r9 is "ARM platform register" ... used as a scratch register
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#define reg_64k r10 /* apple_ii_64k table address */
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// r10 is another scratch variable
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#define reg_vmem_r r11 /* cpu65_vmem_r table address */
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#define reg_vmem_r r11 /* cpu65_vmem_r table address */
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// r12 unused
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// r12 is "ARM Intra-Procedure-call scratch register" ... used as a scratch register
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// r13 ARM SP
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// r13 ARM SP
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// r14 ARM return addr
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// r14 ARM return addr
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// r15 ARM PC
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// r15 ARM PC
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@ -36,10 +36,6 @@
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#define ARM_AF_Bit ...
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#define ARM_AF_Bit ...
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// x86-ish instruction macros for legibility =P
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#define ret mov pc, r14
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#ifdef __aarch64__
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#ifdef __aarch64__
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# error 20150205 ARM 64bit untested!!!
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# error 20150205 ARM 64bit untested!!!
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# define PTR_SHIFT #4 // 4<<1 = 8
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# define PTR_SHIFT #4 // 4<<1 = 8
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132
src/arm/cpu.S
132
src/arm/cpu.S
@ -17,11 +17,6 @@
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#include "misc.h"
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#include "misc.h"
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// debugging is necessary for running CPU test suite and to use the 65c02 debugger
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#ifndef NDEBUG
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#define CPU_DEBUGGING 1
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#endif
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#define DecodeFlags \
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#define DecodeFlags \
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ldr r1, SYM(cpu65_flags_decode); \
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ldr r1, SYM(cpu65_flags_decode); \
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ldrb F_Reg, [r1, r0];
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ldrb F_Reg, [r1, r0];
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@ -51,7 +46,6 @@
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ldr r1, SYM(cpu65_f); \
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ldr r1, SYM(cpu65_f); \
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strb r0, [r1]
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strb r0, [r1]
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// Tracing is necessary for some CPU tests and to verify operation against other emulators
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// Tracing is necessary for some CPU tests and to verify operation against other emulators
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#if CPU_TRACING
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#if CPU_TRACING
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# define TRACE_PROLOGUE \
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# define TRACE_PROLOGUE \
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@ -65,10 +59,10 @@
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# define TRACE_ARG2 \
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# define TRACE_ARG2 \
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bl CALL(cpu65_trace_arg2);
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bl CALL(cpu65_trace_arg2);
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# define TRACE_EPILOGUE \
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# define TRACE_EPILOGUE \
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push {r0}; \
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CommonSaveCPUState; \
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CommonSaveCPUState; \
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push {r0, EffectiveAddr, PC_Reg, lr}; \
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bl CALL(cpu65_trace_epilogue); \
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bl CALL(cpu65_trace_epilogue); \
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pop {r0};
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pop {r0, EffectiveAddr, PC_Reg, lr};
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#else
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#else
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# define TRACE_PROLOGUE
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# define TRACE_PROLOGUE
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# define TRACE_ARG
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# define TRACE_ARG
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@ -78,50 +72,57 @@
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#endif
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#endif
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#if CPU_DEBUGGING
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#define CPUStatsReset \
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# define CPU_DEBUGGING_RESET \
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ldr r1, SYM(cpu65_opcode); \
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ldr r1, SYM(cpu65_opcode); \
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strb r0, [r1]; /* r0 should be next opcode */ \
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strb r0, [r1]; /* r0 should be next opcode */ \
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eor r9, r9, r9; \
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eor r9, r9, r9; \
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ldr r1, SYM(cpu65_opcycles); \
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ldr r1, SYM(cpu65_opcycles); \
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strb r9, [r1]; \
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strb r9, [r1]; \
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/*ldr r1, SYM(cpu65_rw);*/ \
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ldr r1, SYM(cpu65_rw); \
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strb r9, [r1];
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strb r9, [r1];
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# define CPU_DEBUGGING_SET_READ \
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#define CPUStatsSetRead \
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/*ldr r1, SYM(cpu65_rw);*/ \
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ldr r1, SYM(cpu65_rw); \
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ldrb r9, [r1]; \
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ldrb r9, [r1]; \
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orr r9, r9, #1; \
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orr r9, r9, #1; \
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strb r9, [r1];
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strb r9, [r1];
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# define CPU_DEBUGGING_SET_WRITE \
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/*ldr r1, SYM(cpu65_rw);*/ \
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#define CPUStatsSetWrite \
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ldr r1, SYM(cpu65_rw); \
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ldrb r9, [r1]; \
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ldrb r9, [r1]; \
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orr r9, r9, #2; \
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orr r9, r9, #2; \
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strb r9, [r1]; \
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strb r9, [r1]; \
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ldr r1, SYM(cpu65_d); \
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ldr r1, SYM(cpu65_d); \
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strb r0, [r1];
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strb r0, [r1];
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#else
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# define CPU_DEBUGGING_SET_READ
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# define CPU_DEBUGGING_RESET
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# define CPU_DEBUGGING_SET_WRITE
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#endif
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// CPU (6502) helper macros
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// CPU (6502) helper macros
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// Add 16bit x with <=16bit amt
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#define AddUint16(x, amt) \
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#define AddUint16(x, amt) \
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add x, x, amt; \
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add x, x, amt; \
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bic x, #0x10000;
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bic x, #0x10000;
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// Increment 16bit x
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#define IncUint16(x) \
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#define IncUint16(x) \
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AddUint16(x, #1)
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AddUint16(x, #1)
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#define SubUint16(x, amt) \
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// Add 8bit x with <=8bit amt
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sub x, x, amt; \
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#define AddUint8(x, amt) \
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mov x, x, LSL #16; \
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add x, x, amt; \
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mov x, x, LSR #16;
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bic SP_Reg, #0x0100;
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#define DecUint16(x) \
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// Increment 8bit x
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SubUint16(x, #1)
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#define IncUint8(x) \
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AddUint8(x, #1)
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// Subtract 8bit x by <=8bit amt
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#define SubUint8(x, amt) \
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subs x, x, amt; \
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movmi x, #0xFF;
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// Decrement 8bit x
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#define DecUint8(x) \
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SubUint8(x, #1)
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#define GetFromPC_B \
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#define GetFromPC_B \
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mov EffectiveAddr, PC_Reg; \
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mov EffectiveAddr, PC_Reg; \
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@ -150,13 +151,13 @@
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#define JumpNextInstruction \
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#define JumpNextInstruction \
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TRACE_PROLOGUE \
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TRACE_PROLOGUE \
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GetFromPC_B \
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GetFromPC_B \
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CPU_DEBUGGING_RESET \
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CPUStatsReset \
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ldr r1, SYM(cpu65__opcodes); \
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ldr r1, SYM(cpu65__opcodes); \
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ldr r1, [r1, r0, LSL PTR_SHIFT]; \
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ldr r1, [r1, r0, LSL PTR_SHIFT]; \
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bx r1;
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bx r1;
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#define GetFromEA_B \
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#define GetFromEA_B \
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CPU_DEBUGGING_SET_READ \
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CPUStatsSetRead \
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ldr r1, [reg_vmem_r, EffectiveAddr, LSL PTR_SHIFT]; \
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ldr r1, [reg_vmem_r, EffectiveAddr, LSL PTR_SHIFT]; \
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blx r1;
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blx r1;
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@ -171,7 +172,7 @@
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orr r0, hi_byte, lo_byte;
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orr r0, hi_byte, lo_byte;
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#define PutToEA_B \
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#define PutToEA_B \
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CPU_DEBUGGING_SET_WRITE \
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CPUStatsSetWrite \
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ldr r1, SYM(cpu65_vmem_w); \
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ldr r1, SYM(cpu65_vmem_w); \
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ldr r1, [r1, EffectiveAddr, LSL PTR_SHIFT]; \
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ldr r1, [r1, EffectiveAddr, LSL PTR_SHIFT]; \
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blx r1;
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blx r1;
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@ -200,15 +201,14 @@
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#define pc_hi_next r0
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#define pc_hi_next r0
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#define BranchXCycles \
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#define BranchXCycles \
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ldr mem_cycle_count, SYM(cpu65_opcycles); \
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ldr mem_cycle_count, SYM(cpu65_opcycles); \
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eor scratch_count, scratch_count, scratch_count; /* HACK FIXME TODO VERIFY IN GDB : is this necessary? */ \
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ldrb scratch_count, [mem_cycle_count]; \
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ldrb scratch_count, [mem_cycle_count]; \
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add scratch_count, scratch_count, #1; /* +1 branch taken */ \
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add scratch_count, scratch_count, #1; /* +1 branch taken */ \
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mov pc_hi_prev, PC_Reg; \
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mov pc_hi_prev, PC_Reg; \
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mov pc_hi_prev, pc_hi_prev, LSR #8; \
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mov pc_hi_prev, pc_hi_prev, LSR #8; \
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cbw; \
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cbw; \
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add PC_Reg, PC_Reg, r0; /* branch PC */ \
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add PC_Reg, PC_Reg, r0; /* branch PC */ \
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mov PC_Reg, PC_Reg, LSL #24; /* 16bit under/overflow protection */ \
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mov PC_Reg, PC_Reg, LSL #16; /* 16bit under/overflow protection */ \
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mov PC_Reg, PC_Reg, LSR #24; \
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mov PC_Reg, PC_Reg, LSR #16; \
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mov pc_hi_next, PC_Reg; \
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mov pc_hi_next, PC_Reg; \
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mov pc_hi_next, pc_hi_next, LSR #8; \
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mov pc_hi_next, pc_hi_next, LSR #8; \
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teq pc_hi_next, pc_hi_prev; \
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teq pc_hi_next, pc_hi_prev; \
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@ -266,6 +266,7 @@
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#ifdef APPLE2_VM
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#ifdef APPLE2_VM
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#define RestoreAltZP \
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#define RestoreAltZP \
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ldr stack_loc, SYM(base_stackzp); \
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ldr stack_loc, SYM(base_stackzp); \
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ldr stack_loc, [stack_loc]; \
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add stack_loc, stack_loc, #0x100; \
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add stack_loc, stack_loc, #0x100; \
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add stack_loc, stack_loc, SP_Reg;
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add stack_loc, stack_loc, SP_Reg;
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#else
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#else
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@ -275,16 +276,14 @@
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#define Push(x) \
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#define Push(x) \
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RestoreAltZP \
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RestoreAltZP \
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strb x, [stack_loc]; \
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strb x, [stack_loc]; \
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subs SP_Reg, SP_Reg, #1; \
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DecUint8(SP_Reg)
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movmi SP_Reg, #0xFF;
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#warning TODO FIXME ... need to write a 65c02 stack underflow vm test ... also how does AppleWin handle 65c02 underflow?
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#warning TODO FIXME ... need to write a 65c02 stack_loc underflow vm test ... also how does AppleWin handle 65c02 underflow?
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#define Pop(x) \
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#define Pop(x) \
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add SP_Reg, SP_Reg, #1; \
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IncUint8(SP_Reg) \
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bic SP_Reg, #0x0100; \
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RestoreAltZP \
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RestoreAltZP \
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ldrb x, [stack_loc];
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ldrb x, [stack_loc];
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#warning TODO FIXME ... need to write a 65c02 stack overflow vm test ... also how does AppleWin handle 65c02 underflow?
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#warning TODO FIXME ... need to write a 65c02 stack overflow vm test ... also how does AppleWin handle 65c02 overflow?
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// addressing macros
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// addressing macros
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@ -799,9 +798,6 @@ ENTRY(op_ADC_ind_zpage)
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DoADC_b
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DoADC_b
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Continue
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Continue
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mask_FFFF: .hword 0xFFFF
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interrupt_vector: .hword 0xFFFE
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reset_vector: .hword 0xFFFC
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.ltorg
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.ltorg
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/* ----------------------------------
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/* ----------------------------------
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@ -1088,7 +1084,6 @@ ENTRY(op_BRA)
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ENTRY(op_UNK) /* make undefined opcodes fault */
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ENTRY(op_UNK) /* make undefined opcodes fault */
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ENTRY(op_BRK)
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ENTRY(op_BRK)
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#warning TODO FIXME ... write test for overflow in op_BRK
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IncUint16(PC_Reg)
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IncUint16(PC_Reg)
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mov r0, PC_Reg
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mov r0, PC_Reg
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mov r0, r0, ROR #8
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mov r0, r0, ROR #8
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@ -1465,7 +1460,6 @@ ENTRY(op_JMP_abs_ind_x)
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add EffectiveAddr, r0
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add EffectiveAddr, r0
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mov EffectiveAddr, EffectiveAddr, LSL #24 // 16bit under/overflow protection
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mov EffectiveAddr, EffectiveAddr, LSL #24 // 16bit under/overflow protection
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mov EffectiveAddr, EffectiveAddr, LSR #24
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mov EffectiveAddr, EffectiveAddr, LSR #24
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#warning FIXME TODO write test for op_JMP_abs_ind_x under/overflow protection
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GetFromMem_W(EffectiveAddr)
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GetFromMem_W(EffectiveAddr)
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mov PC_Reg, r0
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mov PC_Reg, r0
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Continue
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Continue
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@ -1475,11 +1469,10 @@ ENTRY(op_JMP_abs_ind_x)
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---------------------------------- */
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---------------------------------- */
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ENTRY(op_JSR) // 0x20
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ENTRY(op_JSR) // 0x20
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#warning TODO FIXME write test for op_JSR underflow ...
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GetAbs
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GetAbs
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mov r0, PC_Reg
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mov r0, PC_Reg
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subs r0, r0, #1
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sub r0, r0, #1
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mov r0, r0, LSL #16 // handle underflow
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mov r0, r0, LSL #16 // handle underflow -- can this happen in second mem page?
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mov r0, r0, ROR #24
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mov r0, r0, ROR #24
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Push(r0) // push hi_byte
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Push(r0) // push hi_byte
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mov r0, r0, LSR #24
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mov r0, r0, LSR #24
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@ -1849,7 +1842,6 @@ ENTRY(op_RTI) // 0x40
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---------------------------------- */
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---------------------------------- */
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ENTRY(op_RTS) // 0x60
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ENTRY(op_RTS) // 0x60
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#warning TODO FIXME write test for this overflow ...
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Pop(lo_byte)
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Pop(lo_byte)
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Pop(hi_byte)
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Pop(hi_byte)
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mov hi_byte, hi_byte, LSL #8
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mov hi_byte, hi_byte, LSL #8
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@ -2323,37 +2315,36 @@ continue:
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ldrb r0, [r0]
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ldrb r0, [r0]
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ldrb cycles_exe, [r1, r0]
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ldrb cycles_exe, [r1, r0]
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ldr r1, SYM(cpu65_opcycles)
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ldr r1, SYM(cpu65_opcycles)
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ldrb r2, [r1]
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ldrb r9, [r1]
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add cycles_exe, cycles_exe, r2
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add cycles_exe, cycles_exe, r9
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strb cycles_exe, [r1]
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strb cycles_exe, [r1]
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TRACE_EPILOGUE
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TRACE_EPILOGUE
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ldr r1, SYM(gc_cycles_timer_0)
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ldr r1, SYM(gc_cycles_timer_0)
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ldr r2, [r1]
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ldr r9, [r1]
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sub r2, r2, cycles_exe
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sub r9, r9, cycles_exe
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str r2, [r1]
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str r9, [r1]
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ldr r1, SYM(gc_cycles_timer_1)
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ldr r1, SYM(gc_cycles_timer_1)
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ldr r2, [r1]
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ldr r9, [r1]
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sub r2, r2, cycles_exe
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sub r9, r9, cycles_exe
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str r2, [r1]
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str r9, [r1]
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ldr r1, SYM(cpu65_cycle_count)
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ldr r1, SYM(cpu65_cycle_count)
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ldr r2, [r1]
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ldr r9, [r1]
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add r2, r2, cycles_exe
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add r9, r9, cycles_exe
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str r2, [r1]
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str r9, [r1]
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ldr r1, SYM(cpu65_cycles_to_execute)
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ldr r1, SYM(cpu65_cycles_to_execute)
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ldr r2, [r1]
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ldr r9, [r1]
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subs r2, r2, cycles_exe
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subs r9, r9, cycles_exe
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str r2, [r1]
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str r9, [r1]
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bmi exit_cpu65_run
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bmi exit_cpu65_run
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beq exit_cpu65_run
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beq exit_cpu65_run
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continue1: eor r0, r0, r0
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continue1: ldr r1, SYM(cpu65__signal)
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ldr r1, SYM(cpu65__signal)
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ldrb r0, [r1]
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ldrb r0, [r1]
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orr r0, r0, r0
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orrs r0, r0, r0
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bne exception
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bne exception
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JumpNextInstruction
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JumpNextInstruction
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@ -2405,8 +2396,9 @@ ex_irq: tst F_Reg, #I_Flag // Already interrupt
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------------------------------------------------------------------------- */
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------------------------------------------------------------------------- */
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ENTRY(cpu65_run)
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ENTRY(cpu65_run)
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||||||
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push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
|
||||||
// Restore CPU state when being called from C.
|
// Restore CPU state when being called from C.
|
||||||
#warning FIXME TODO ... do all the ldrb's zero-out the high-24bits of the destination reg?
|
ldr reg_vmem_r, SYM(cpu65_vmem_r)
|
||||||
ldr r1, SYM(cpu65_ea)
|
ldr r1, SYM(cpu65_ea)
|
||||||
ldrh EffectiveAddr, [r1]
|
ldrh EffectiveAddr, [r1]
|
||||||
ldr r1, SYM(cpu65_pc)
|
ldr r1, SYM(cpu65_pc)
|
||||||
@ -2439,7 +2431,7 @@ exit_cpu65_run:
|
|||||||
ldr r1, SYM(cpu65_pc)
|
ldr r1, SYM(cpu65_pc)
|
||||||
strh PC_Reg, [r1]
|
strh PC_Reg, [r1]
|
||||||
CommonSaveCPUState
|
CommonSaveCPUState
|
||||||
ret
|
pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
|
||||||
|
|
||||||
exit_reinit: ldr r1, SYM(cpu65__signal)
|
exit_reinit: ldr r1, SYM(cpu65__signal)
|
||||||
mov r0, #0
|
mov r0, #0
|
||||||
@ -2447,7 +2439,7 @@ exit_reinit: ldr r1, SYM(cpu65__signal)
|
|||||||
ldr r1, SYM(emul_reinitialize)
|
ldr r1, SYM(emul_reinitialize)
|
||||||
mov r0, #1
|
mov r0, #1
|
||||||
strb r0, [r1]
|
strb r0, [r1]
|
||||||
ret
|
pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
|
||||||
|
|
||||||
/* -------------------------------------------------------------------------
|
/* -------------------------------------------------------------------------
|
||||||
Debugger hooks
|
Debugger hooks
|
||||||
@ -2457,5 +2449,9 @@ ENTRY(cpu65_direct_write)
|
|||||||
#warning FIXME TODO implement cpu65_direct_write ...
|
#warning FIXME TODO implement cpu65_direct_write ...
|
||||||
mov r0, #42
|
mov r0, #42
|
||||||
ldr r0, [r0] // segfault
|
ldr r0, [r0] // segfault
|
||||||
ret
|
mov pc, lr
|
||||||
|
|
||||||
|
interrupt_vector: .hword 0xFFFE
|
||||||
|
reset_vector: .hword 0xFFFC
|
||||||
|
.ltorg
|
||||||
|
|
||||||
|
|||||||
@ -16,49 +16,49 @@
|
|||||||
ENTRY(func) ldr r1, SYM(softswitches); \
|
ENTRY(func) ldr r1, SYM(softswitches); \
|
||||||
ldr r0, [r1]; \
|
ldr r0, [r1]; \
|
||||||
tst r0, $SS_CXROM; \
|
tst r0, $SS_CXROM; \
|
||||||
bne 1f; \
|
beq 1f; \
|
||||||
ldr r1, SYM(pointer); \
|
ldr r1, SYM(pointer); \
|
||||||
blx r1; \
|
ldr r1, [r1]; \
|
||||||
ret; \
|
|
||||||
1: ldr r1, SYM(pointer); \
|
|
||||||
ldrb r0, [r1, EffectiveAddr]; \
|
ldrb r0, [r1, EffectiveAddr]; \
|
||||||
ret;
|
mov pc, lr; \
|
||||||
|
1: ldr r1, SYM(pointer); \
|
||||||
|
push {lr}; \
|
||||||
|
blx r1; \
|
||||||
|
pop {pc}; \
|
||||||
|
|
||||||
#define GLUE_BANK_READ(func,pointer) \
|
#define GLUE_BANK_READ(func,pointer) \
|
||||||
ENTRY(func) ldr r1, SYM(pointer); \
|
ENTRY(func) ldr r1, SYM(pointer); \
|
||||||
|
ldr r1, [r1]; \
|
||||||
ldrb r0, [r1, EffectiveAddr]; \
|
ldrb r0, [r1, EffectiveAddr]; \
|
||||||
ret;
|
mov pc, lr;
|
||||||
|
|
||||||
#define GLUE_BANK_WRITE(func,pointer) \
|
#define GLUE_BANK_WRITE(func,pointer) \
|
||||||
ENTRY(func) ldr r1, SYM(pointer); \
|
ENTRY(func) ldr r1, SYM(pointer); \
|
||||||
|
ldr r1, [r1]; \
|
||||||
strb r0, [r1, EffectiveAddr]; \
|
strb r0, [r1, EffectiveAddr]; \
|
||||||
ret;
|
mov pc, lr;
|
||||||
|
|
||||||
#define GLUE_BANK_MAYBEWRITE(func,pointer) \
|
#define GLUE_BANK_MAYBEWRITE(func,pointer) \
|
||||||
ENTRY(func) ldr r1, SYM(pointer); \
|
ENTRY(func) ldr r1, SYM(pointer); \
|
||||||
cmp r1, #0; \
|
ldr r1, [r1]; \
|
||||||
beq 1f; \
|
tst r1, #0; \
|
||||||
strb r0, [r1, EffectiveAddr]; \
|
strneb r0, [r1, EffectiveAddr]; \
|
||||||
1: ret;
|
mov pc, lr;
|
||||||
|
|
||||||
|
|
||||||
#define GLUE_C_WRITE(func) \
|
#define GLUE_C_WRITE(func) \
|
||||||
ENTRY(func) push {r0, PC_Reg, SP_Reg, F_Reg, Y_Reg, X_Reg, A_Reg}; \
|
ENTRY(func) push {r0, PC_Reg, SP_Reg, F_Reg, Y_Reg, X_Reg, A_Reg, lr}; \
|
||||||
and r0, #0xff; \
|
and r0, #0xff; \
|
||||||
mov r1, r0; \
|
mov r1, r0; \
|
||||||
mov r0, EffectiveAddr; \
|
mov r0, EffectiveAddr; \
|
||||||
bl CALL(c_##func); \
|
bl CALL(c_##func); \
|
||||||
pop {r0, PC_Reg, SP_Reg, F_Reg, Y_Reg, X_Reg, A_Reg}; \
|
pop {r0, PC_Reg, SP_Reg, F_Reg, Y_Reg, X_Reg, A_Reg, pc};
|
||||||
ret;
|
|
||||||
|
|
||||||
#define _GLUE_C_READ(func, ...) \
|
#define GLUE_C_READ(func) \
|
||||||
ENTRY(func) push {PC_Reg, SP_Reg, F_Reg, Y_Reg, X_Reg, A_Reg}; \
|
ENTRY(func) push {PC_Reg, SP_Reg, F_Reg, Y_Reg, X_Reg, A_Reg, lr}; \
|
||||||
mov r0, EffectiveAddr; \
|
mov r0, EffectiveAddr; \
|
||||||
bl CALL(c_##func); \
|
bl CALL(c_##func); \
|
||||||
pop {PC_Reg, SP_Reg, F_Reg, Y_Reg, X_Reg, A_Reg}; \
|
pop {PC_Reg, SP_Reg, F_Reg, Y_Reg, X_Reg, A_Reg, pc};
|
||||||
__VA_ARGS__ \
|
|
||||||
ret;
|
|
||||||
|
|
||||||
#define GLUE_C_READ(FUNC) _GLUE_C_READ(FUNC)
|
#define GLUE_C_READ_ALTZP(FUNC) GLUE_C_READ(FUNC)
|
||||||
#define GLUE_C_READ_ALTZP(FUNC) _GLUE_C_READ(FUNC)
|
|
||||||
|
|
||||||
|
|||||||
Loading…
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Reference in New Issue
Block a user