mirror of
https://github.com/mauiaaron/apple2.git
synced 2024-12-24 02:33:19 +00:00
switch internal/peripheral rom on CXROM flag
* fixes a bug where op_BRK doesn't work when Mockingboard installed * this is still hackish and hardcoded ... ultimately we need an interface to add/remove virtual peripherals
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0cc0db17b2
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@ -15,7 +15,8 @@
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*/
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#define __ASSEMBLY__
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#include <apple2.h>
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#include "apple2.h"
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#include "misc.h"
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#define GLUE_FIXED_READ(func,address) \
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E(func) movb SN(address)(%edi),%al; \
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@ -25,6 +26,16 @@ E(func) movb SN(address)(%edi),%al; \
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E(func) movb %al,SN(address)(%edi); \
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ret;
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#define GLUE_BANK_MAYBEREAD(func,pointer) \
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E(func) testl $SS_CXROM, SN(softswitches); \
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jnz 1f; \
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call *SN(pointer); \
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ret; \
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1: addl SN(pointer),%edi; \
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movb (%edi),%al; \
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subl SN(pointer),%edi; \
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ret;
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#define GLUE_BANK_READ(func,pointer) \
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E(func) addl SN(pointer),%edi; \
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movb (%edi),%al; \
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@ -17,6 +17,7 @@
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#define GLUE_FIXED_READ(func,address)
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#define GLUE_FIXED_WRITE(func,address)
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#define GLUE_BANK_READ(func,pointer)
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#define GLUE_BANK_MAYBEREAD(func,pointer)
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#define GLUE_BANK_WRITE(func,pointer)
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#define GLUE_BANK_MAYBEWRITE(func,pointer)
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@ -922,6 +922,8 @@ E(iie_check_c3rom)
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E(iie_cxrom_peripheral)
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andl $~SS_CXROM, SN(softswitches)
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movl $SN(apple_ii_64k), SN(base_cxrom)
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movl $SN(MB_Read), SN(base_c4rom)
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movl $SN(MB_Read), SN(base_c5rom) // HACK FIXME -- MB is hardcoded, what about Phasor?
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testl $SS_C3ROM, SN(softswitches)
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jnz 1f
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movl $SN(apple_ii_64k), SN(base_c3rom)
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@ -931,6 +933,8 @@ E(iie_cxrom_internal)
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orl $SS_CXROM, SN(softswitches)
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movl $SN(apple_ii_64k)+BANK2, SN(base_cxrom)
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movl $SN(apple_ii_64k)+BANK2, SN(base_c3rom)
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movl $SN(apple_ii_64k)+BANK2, SN(base_c4rom)
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movl $SN(apple_ii_64k)+BANK2, SN(base_c5rom)
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ret
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E(iie_check_cxrom)
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22
src/misc.c
22
src/misc.c
@ -69,6 +69,8 @@ GLUE_BANK_READ(iie_read_ram_zpage_and_stack,base_stackzp)
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GLUE_BANK_WRITE(iie_write_ram_zpage_and_stack,base_stackzp)
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GLUE_BANK_READ(iie_read_slot3,base_c3rom)
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GLUE_BANK_MAYBEREAD(iie_read_slot4,base_c4rom)
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GLUE_BANK_MAYBEREAD(iie_read_slot5,base_c5rom)
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GLUE_BANK_READ(iie_read_slotx,base_cxrom)
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@ -220,7 +222,7 @@ void c_initialize_tables() {
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write_unmapped_softswitch;
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}
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/* slot rom */
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/* slot rom defaults */
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for (i = 0xC100; i < 0xD000; i++)
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{
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cpu65_vmem[i].r =
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@ -483,10 +485,22 @@ void c_initialize_tables() {
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iie_read_slot3; /* slot 3 (80col) */
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}
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for (i = 0xC400; i < 0xC800; i++)
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for (i = 0xC400; i < 0xC500; i++)
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{
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cpu65_vmem[i].r =
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iie_read_slotx; /* slots 4 - 7 (x) */
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iie_read_slot4; /* slot 4 - MB or Phasor */
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}
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for (i = 0xC500; i < 0xC600; i++)
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{
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cpu65_vmem[i].r =
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iie_read_slot5; /* slot 5 - MB #2 */
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}
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for (i = 0xC600; i < 0xC800; i++)
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{
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cpu65_vmem[i].r =
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iie_read_slotx; /* slots 6 - 7 (x) */
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}
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for (i = 0xC800; i < 0xD000; i++)
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@ -662,6 +676,8 @@ void c_initialize_iie_switches() {
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base_hgrwrt= apple_ii_64k[0];
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base_c3rom = apple_ii_64k[1]; /* c3rom internal */
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base_c4rom = apple_ii_64k[1]; /* c4rom internal */
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base_c5rom = apple_ii_64k[1]; /* c5rom internal */
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c8rom_offset = 0x10000; /* c8rom internal */
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base_cxrom = apple_ii_64k[0]; /* cxrom peripheral */
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}
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@ -194,6 +194,8 @@ iie_write_screen_hole_hires_page0(),
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iie_read_ram_zpage_and_stack(),
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iie_write_ram_zpage_and_stack(),
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iie_read_slot3(),
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iie_read_slot4(),
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iie_read_slot5(),
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iie_read_slotx(),
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iie_read_slot_expansion(),
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iie_disable_slot_expansion(),
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@ -1945,7 +1945,7 @@ static void RegisterIoHandler(UINT uSlot, iofunction IOReadC0, iofunction IOWrit
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base_addr = 0xC000 + (uSlot<<8); // uSlot == 4 => 0xC400 , uSlot == 5 => 0xC500
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for (unsigned int i = 0; i < 0x100; i++)
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{
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cpu65_vmem[base_addr+i].r = IOReadCx;
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//cpu65_vmem[base_addr+i].r = IOReadCx; -- CANNOT DO THIS HERE -- DEPENDS ON cxrom softswitch
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cpu65_vmem[base_addr+i].w = IOWriteCx;
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}
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}
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