mirror of
https://github.com/mauiaaron/apple2.git
synced 2024-11-19 11:31:13 +00:00
First cut at 65c02 implemented on aarch64
This commit is contained in:
Aaron Culliney
parent
4e27c1a322
commit
43d99ec9f4
@ -1,4 +1,4 @@
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APP_ABI := armeabi-v7a x86 x86_64
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APP_ABI := armeabi-v7a arm64-v8a x86 x86_64
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# Do not change APP_PLATFORM if we care about Gingerbread (2.3.3) devices! We must compile against android-10,
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# otherwise we may encounter runtime load-library errors from symbols that should have been inlined against older
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@ -148,7 +148,7 @@ if test "x$do_build" = "x1" -o "x$do_release" = "x1" ; then
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# Symbolicate and move symbols file into location to be deployed on device
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SYMFILE=libapple2ix.so.sym
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ARCHES_TO_SYMBOLICATE='armeabi-v7a x86 x86_64'
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ARCHES_TO_SYMBOLICATE='armeabi-v7a arm64-v8a x86 x86_64'
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for arch in $ARCHES_TO_SYMBOLICATE ; do
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SYMDIR=../assets/symbols/$arch/libapple2ix.so
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@ -63,7 +63,7 @@ APPLE2_MAIN_SRC = \
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$(APPLE2_SRC_PATH)/zlib-helpers.c \
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$(APPLE2_SRC_PATH)/../externals/jsmn/jsmn.c
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APPLE2_OPTIM_CFLAGS := -Os
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APPLE2_OPTIM_CFLAGS := -O2 # match the same optimization level as BUILD_MODE=release for ndk-build
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APPLE2_BASE_CFLAGS := -DAPPLE2IX=1 -DINTERFACE_TOUCH=1 -DMOBILE_DEVICE=1 -DVIDEO_OPENGL=1 -std=gnu11 -fPIC $(APPLE2_OPTIM_CFLAGS) -I$(APPLE2_SRC_PATH)
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APPLE2_BASE_LDLIBS := -Wl,-z,text -Wl,-z,noexecstack -llog -landroid -lGLESv2 -lz -lOpenSLES -latomic
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@ -15,45 +15,107 @@
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#include "cpu.h"
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#include "glue-offsets.h"
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// ARM register mappings
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// r0, r1 are scratch regs, with r0 generally as the "important byte"
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#define EffectiveAddr r2 /* 16bit Effective address */
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#define PC_Reg r3 /* 16bit 6502 Program Counter */
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#define SP_Reg r4 /* 16bit 6502 Stack pointer */
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#define F_Reg r5 /* 8bit 6502 flags */
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#define Y_Reg r6 /* 8bit 6502 Y register */
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#define X_Reg r7 /* 8bit 6502 X register */
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#define A_Reg r8 /* 8bit 6502 A register */
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// r9 is "ARM platform register" ... used as a scratch register
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#define reg_args r10 /* cpu65_run() args register */
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#define reg_vmem_r r11 /* cpu65_vmem_r table address */
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// r12 is "ARM Intra-Procedure-call scratch register" ... used as a scratch register
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// r13 ARM SP
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// r14 ARM return addr
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// r15 ARM PC
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#ifdef __aarch64__
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# error 20150205 ARM 64bit untested!!!
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# define PTR_SHIFT #4 // 4<<1 = 8
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# define ROR_BIT 0x8000000000000000
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#else
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# define PTR_SHIFT #2 // 2<<1 = 4
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# define ROR_BIT 0x80000000
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#endif
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#if !defined(__APPLE__)
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# define NO_UNDERSCORES 1
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# define STRBNE strneb
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#endif
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// ARM register mappings
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#define bz beq
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#define bnz bne
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#define ROR_BIT 0x80000000
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#ifdef __aarch64__
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# define DOT_ARM
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# define ALIGN .align 2;
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# define PTR_SHIFT #3 // 1<<3 = 8
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# define BLX blr
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# define BX br
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// x: 64bit addressing mode
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// w: 32bit addressing mode
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# define xr0 x0 /* scratch/"important byte" */
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# define wr0 w0 /* scratch/"important byte" */
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# define xr1 x1 /* scratch */
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# define wr1 w1 /* scratch */
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# define wr9 w2
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// NOTE: ARMv8 Procedure Call Standard indicates that x19-x28 are callee saved ... so we can call back into C without needing to
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// first save these ...
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# define xEffectiveAddr x19 /* 16bit Effective address */
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# define EffectiveAddr w19 /* 16bit Effective address */
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# define PC_Reg w20 /* 16bit 6502 Program Counter */
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# define xSP_Reg x21 /* 16bit 6502 Stack pointer */
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# define SP_Reg w21 /* 16bit 6502 Stack pointer */
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# define xF_Reg x22 /* 8bit 6502 flags */
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# define F_Reg w22 /* 8bit 6502 flags */
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# define Y_Reg w23 /* 8bit 6502 Y register */
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# define X_Reg w24 /* 8bit 6502 X register */
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# define A_Reg w25 /* 8bit 6502 A register */
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# define xA_Reg x25 /* 8bit 6502 A register */
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# define reg_args x26 /* cpu65_run() args register */
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# define reg_vmem_r x27 /* cpu65_vmem_r table address */
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# define xr12 x28 /* scratch */
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# define wr12 w28 /* scratch */
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// x29 : frame pointer (callee-saved)
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// x30 : return address
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// xzr/wzr : zero register
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// sp : stack pointer
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// pc : instruction pointer
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#else
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# define STRBNE strbne
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# define DOT_ARM .arm;
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# define ALIGN .balign 4;
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# define PTR_SHIFT #2 // 1<<2 = 4
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# define BLX blx
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# define BX bx
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// r0, r1 are scratch regs, with r0 generally as the "important byte"
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# define xr0 r0 /* scratch/"important byte" */
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# define wr0 r0 /* scratch/"important byte" */
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# define xr1 r1 /* scratch */
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# define wr1 r1 /* scratch */
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# define wr9 r9 /* scratch */
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// r12 is "ARM Intra-Procedure-call scratch register" ... used as a scratch register
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# define xr12 r12 /* scratch */
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# define wr12 r12 /* scratch */
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// NOTE: these need to be preserved in subroutine (C) invocations ... */
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# define EffectiveAddr r2 /* 16bit Effective address */
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# define xEffectiveAddr r2 /* 16bit Effective address */
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# define PC_Reg r3 /* 16bit 6502 Program Counter */
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// NOTE: ARMv7 PCS states : "A subroutine must preserve the contents of the registers r4-r8, r10, r11 and SP [...]"
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# define xSP_Reg r4 /* 16bit 6502 Stack pointer */
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# define SP_Reg r4 /* 16bit 6502 Stack pointer */
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# define xF_Reg r5 /* 8bit 6502 flags */
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# define F_Reg r5 /* 8bit 6502 flags */
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# define Y_Reg r6 /* 8bit 6502 Y register */
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# define X_Reg r7 /* 8bit 6502 X register */
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# define A_Reg r8 /* 8bit 6502 A register */
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# define xA_Reg r8 /* 8bit 6502 A register */
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// r9 is "ARM platform register" ... used as a scratch register
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# define reg_args r10 /* cpu65_run() args register */
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# define reg_vmem_r r11 /* cpu65_vmem_r table address */
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// r13 ARM SP
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// r14 ARM LR (return addr)
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// r15 ARM PC
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#endif
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#if NO_UNDERSCORES
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# define ENTRY(x) .globl x; .arm; .balign 4; x##:
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# define ENTRY(x) .global x; DOT_ARM ALIGN x##:
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# define CALL(x) x
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#else
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# define ENTRY(x) .globl _##x; .arm; .balign 4; _##x##:
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# define ENTRY(x) .global _##x; DOT_ARM ALIGN _##x##:
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# define CALL(x) _##x
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#endif
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1072
src/arm/cpu.S
1072
src/arm/cpu.S
File diff suppressed because it is too large
Load Diff
53
src/arm/glue-offsets64.h
Normal file
53
src/arm/glue-offsets64.h
Normal file
@ -0,0 +1,53 @@
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/* This file is auto-generated for a specific architecture ABI */
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#define UNUSED0 0
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#define CPU65_TRACE_PROLOGUE 8
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#define CPU65_TRACE_ARG 16
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#define UNUSED1 24
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#define UNUSED2 32
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#define CPU65_TRACE_EPILOGUE 40
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#define CPU65_TRACE_IRQ 48
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#define DEBUG_ILLEGAL_BCD 56
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#define CPU65_VMEM_R 64
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#define CPU65_VMEM_W 72
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#define CPU65_FLAGS_ENCODE 80
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#define CPU65_FLAGS_DECODE 88
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#define CPU65__OPCODES 96
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#define CPU65__OPCYCLES 104
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#define BASE_RAMRD 112
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#define BASE_RAMWRT 120
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#define BASE_TEXTRD 128
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#define BASE_TEXTWRT 136
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#define BASE_HGRRD 144
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#define BASE_HGRWRT 152
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#define BASE_STACKZP 160
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#define BASE_D000_RD 168
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#define BASE_E000_RD 176
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#define BASE_D000_WRT 184
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#define BASE_E000_WRT 192
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#define BASE_C3ROM 200
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#define BASE_C4ROM 208
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#define BASE_C5ROM 216
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#define BASE_CXROM 224
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#define SOFTSWITCHES 232
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#define GC_CYCLES_TIMER_0 236
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#define GC_CYCLES_TIMER_1 240
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#define CPU65_CYCLES_TO_EXECUTE 244
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#define CPU65_CYCLE_COUNT 248
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#define UNUSED3 252
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#define INTERRUPT_VECTOR 256
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#define RESET_VECTOR 258
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#define CPU65_PC 260
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#define CPU65_EA 262
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#define CPU65_A 264
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#define CPU65_F 265
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#define CPU65_X 266
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#define CPU65_Y 267
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#define CPU65_SP 268
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#define CPU65_D 269
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#define CPU65_RW 270
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#define CPU65_OPCODE 271
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#define CPU65_OPCYCLES 272
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#define CPU65__SIGNAL 273
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#define JOY_BUTTON0 274
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#define JOY_BUTTON1 275
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#define EMUL_REINITIALIZE 276
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@ -12,79 +12,120 @@
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#include "vm.h"
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#include "cpu-regs.h"
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#if __aarch64__
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# define _GLUE_REG_SAVE \
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stp x29, x30, [sp, -16]!;
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# define _GLUE_REG_RESTORE \
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ldp x29, x30, [sp], 16; \
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ret
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# define _GLUE_REG_SAVE0 \
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stp x0, x30, [sp, -16]!;
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# define _GLUE_REG_RESTORE0 \
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ldp x0, x30, [sp], 16; \
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ret
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# define _GLUE_RET \
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ret
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#else
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# define _GLUE_REG_SAVE \
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push {EffectiveAddr, PC_Reg, lr};
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# define _GLUE_REG_RESTORE \
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pop {EffectiveAddr, PC_Reg, pc};
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# define _GLUE_REG_SAVE0 \
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push {r0, EffectiveAddr, PC_Reg, lr};
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# define _GLUE_REG_RESTORE0 \
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pop {r0, EffectiveAddr, PC_Reg, pc};
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# define _GLUE_RET \
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mov pc, lr;
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#endif
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#define GLUE_EXTERN_C_READ(func)
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#define _GLUE_BANK_MAYBE_READ_CX(func,x,pointer) \
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ENTRY(func) ldr r0, [reg_args, #SOFTSWITCHES]; \
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ldr r1, [reg_args, x ## pointer]; \
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tst r0, $SS_CXROM; \
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bne 1f; \
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push {EffectiveAddr, PC_Reg, lr}; \
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blx r1; \
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pop {EffectiveAddr, PC_Reg, pc}; \
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1: ldrb r0, [r1, EffectiveAddr]; \
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mov pc, lr;
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ENTRY(func) ldr wr0, [reg_args, #SOFTSWITCHES]; \
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ldr xr1, [reg_args, x ## pointer]; \
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tst wr0, #SS_CXROM; \
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bnz 1f; \
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_GLUE_REG_SAVE; \
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BLX xr1; \
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_GLUE_REG_RESTORE; \
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1: ldrb wr0, [xr1, xEffectiveAddr]; \
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_GLUE_RET
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#define GLUE_BANK_MAYBE_READ_CX(func,pointer) _GLUE_BANK_MAYBE_READ_CX(func,#,pointer)
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#define _GLUE_BANK_MAYBE_READ_C3(func,x,pointer) \
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ENTRY(func) ldr r0, [reg_args, #SOFTSWITCHES]; \
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ldr r1, [reg_args, x ## pointer]; \
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tst r0, $SS_CXROM; \
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bne 1f; \
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tst r0, $SS_C3ROM; \
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bne 1f; \
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push {EffectiveAddr, PC_Reg, lr}; \
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blx r1; \
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pop {EffectiveAddr, PC_Reg, pc}; \
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1: ldrb r0, [r1, EffectiveAddr]; \
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mov pc, lr;
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ENTRY(func) ldr wr0, [reg_args, #SOFTSWITCHES]; \
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ldr xr1, [reg_args, x ## pointer]; \
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tst wr0, #SS_CXROM; \
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bnz 1f; \
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tst wr0, #SS_C3ROM; \
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bnz 1f; \
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_GLUE_REG_SAVE; \
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BLX xr1; \
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_GLUE_REG_RESTORE; \
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1: ldrb wr0, [xr1, xEffectiveAddr]; \
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_GLUE_RET
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#define GLUE_BANK_MAYBE_READ_C3(func,pointer) _GLUE_BANK_MAYBE_READ_C3(func,#,pointer)
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#define _GLUE_BANK_READ(func,x,pointer) \
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ENTRY(func) ldr r1, [reg_args, x ## pointer]; \
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ldrb r0, [r1, EffectiveAddr]; \
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mov pc, lr;
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ENTRY(func) ldr xr1, [reg_args, x ## pointer]; \
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ldrb wr0, [xr1, xEffectiveAddr]; \
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_GLUE_RET
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#define GLUE_BANK_READ(func,pointer) _GLUE_BANK_READ(func,#,pointer)
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#define _GLUE_BANK_WRITE(func,x,pointer) \
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ENTRY(func) ldr r1, [reg_args, x ## pointer]; \
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strb r0, [r1, EffectiveAddr]; \
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mov pc, lr;
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ENTRY(func) ldr xr1, [reg_args, x ## pointer]; \
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strb wr0, [xr1, xEffectiveAddr]; \
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_GLUE_RET
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#define GLUE_BANK_WRITE(func,pointer) _GLUE_BANK_WRITE(func,#,pointer)
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#define _GLUE_BANK_MAYBEWRITE(func,x,pointer) \
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ENTRY(func) ldr r1, [reg_args, x ## pointer]; \
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teq r1, #0; \
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STRBNE r0, [r1, EffectiveAddr]; \
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mov pc, lr;
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ENTRY(func) ldr xr1, [reg_args, x ## pointer]; \
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eor xr12, xr12, xr12; \
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eor xr1, xr1, xr12; \
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cmp xr1, #0; \
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bz 1f; \
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strb wr0, [xr1, xEffectiveAddr]; \
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1: _GLUE_RET
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#define GLUE_BANK_MAYBEWRITE(func,pointer) _GLUE_BANK_MAYBEWRITE(func,#,pointer)
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#define _GLUE_INLINE_READ(func,x,off) \
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ENTRY(func) ldrb r0, [reg_args, x ## off]; \
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mov pc, lr;
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ENTRY(func) ldrb wr0, [reg_args, x ## off]; \
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_GLUE_RET
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#define GLUE_INLINE_READ(func,off) _GLUE_INLINE_READ(func,#,off)
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#define GLUE_C_WRITE(func) \
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ENTRY(func) push {r0, EffectiveAddr, PC_Reg, lr}; \
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and r0, r0, #0xff; \
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mov r1, r0; \
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mov r0, EffectiveAddr; \
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ENTRY(func) _GLUE_REG_SAVE0; \
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and wr0, wr0, #0xff; \
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mov wr1, wr0; \
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mov wr0, EffectiveAddr; \
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bl CALL(c_##func); \
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pop {r0, EffectiveAddr, PC_Reg, pc};
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_GLUE_REG_RESTORE0;
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#define GLUE_C_READ(func) \
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ENTRY(func) push {EffectiveAddr, PC_Reg, lr}; \
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mov r0, EffectiveAddr; \
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ENTRY(func) _GLUE_REG_SAVE; \
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mov wr0, EffectiveAddr; \
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bl CALL(c_##func); \
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pop {EffectiveAddr, PC_Reg, pc};
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_GLUE_REG_RESTORE;
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#define GLUE_C_READ_ALTZP(FUNC) GLUE_C_READ(FUNC)
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@ -87,7 +87,7 @@ void cpu65_trace_checkpoint(void);
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# define D_Flag 0x20 /* 6502 Decimal mode */
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# define Z_Flag 0x40 /* 6502 Zero */
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# define N_Flag 0x80 /* 6502 Negative */
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#elif defined(__arm__)
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#elif defined(__arm__) || defined(__aarch64__)
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// VCZN positions match positions of shifted status register
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# define V_Flag 0x1
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# define C_Flag 0x2
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@ -101,10 +101,7 @@ void cpu65_trace_checkpoint(void);
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# define I_Flag 0x20
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# define B_Flag 0x40
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# define D_Flag 0x80
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# define BX_Flags 0x50
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# define BI_Flags 0x60
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#elif defined(__aarch64__)
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# error soon ...
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#else
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# error unknown machine architecture
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#endif
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@ -186,7 +186,7 @@ typedef struct cpu65_run_args_s {
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#define OUTPUT_CPU65_RW() printf("#define CPU65_RW %ld\n", offsetof(cpu65_run_args_s, cpu65_rw))
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uint8_t cpu65_opcode; // Last opcode
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#define OUTPUT_CPU65_OPCODE() printf("#define CPU65_OPCODE %ld\n", offsetof(cpu65_run_args_s, cpu65_opcode))
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uint8_t cpu65_opcycles; // Last opcode extra cycles
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uint8_t cpu65_opcycles; // Last opcode cycles
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#define OUTPUT_CPU65_OPCYCLES() printf("#define CPU65_OPCYCLES %ld\n", offsetof(cpu65_run_args_s, cpu65_opcycles))
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uint8_t cpu65__signal;
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