From 46f8e711f67d0e8e7fb0a2e41a62d5294ac41824 Mon Sep 17 00:00:00 2001
From: Aaron Culliney <asc_at_bitr0t_com>
Date: Sat, 14 Jun 2014 10:34:24 -0700
Subject: [PATCH] tweak comments

---
 src/cpu.h  | 2 +-
 src/misc.h | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/cpu.h b/src/cpu.h
index dd9bf80a..75206d37 100644
--- a/src/cpu.h
+++ b/src/cpu.h
@@ -100,7 +100,7 @@ extern int16_t cpu65_cycles_to_execute;
 #define N_Flag_Bit      15              /* 6502 Neg                */
 
 /*
- * These are the 6502 Flags bit positions
+ * 6502 flags bit mask
  */
 #define C_Flag_6502     0x1         // [C]arry
 #define Z_Flag_6502     0x2         // [Z]ero
diff --git a/src/misc.h b/src/misc.h
index 48ab59c5..83da452b 100644
--- a/src/misc.h
+++ b/src/misc.h
@@ -79,8 +79,8 @@ extern uint32_t softswitches;
 #define         SS_PAGE2        0x00000008
 #define         SS_BANK2        0x00000010
 #define         SS_LCRAM        0x00000020
-#define         SS_LCSEC        0x00000040 /* check for double read */
-#define         SS_LCWRT        0x00000080 /* LC write enable */
+#define         SS_LCSEC        0x00000040 /* Pseudo-softswitch : enabled if 2+ reads have occurred */
+#define         SS_LCWRT        0x00000080 /* Pseudo-softswitch : LC write enable */
 #define         SS_80STORE      0x00000100
 #define         SS_80COL        0x00000200
 #define         SS_RAMRD        0x00000400