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Fixes for ADC_b and AND on ARM
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41b8ca7700
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@ -225,7 +225,24 @@
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#define arm_flags r12
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#define lahf \
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/* Virtual x86: Load %AH (r12) from ARM CPU Flags */ \
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mov arm_flags, r15, LSR #28;
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mrs arm_flags, APSR; \
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mov arm_flags, arm_flags, LSR #28;
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#define bt \
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/* Virtual x86: Bit Test (and set ... carry flag only) */ \
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tst F_Reg, #C_Flag; \
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mrs arm_flags, APSR; \
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biceq arm_flags, arm_flags, #0x20000000; \
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orrne arm_flags, arm_flags, #0x20000000; \
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msr APSR_nzcvq, arm_flags;
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#define btc \
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/* Virtual x86: Bit Test and Clear (carry flag only) */ \
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tst F_Reg, #C_Flag; \
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mrs arm_flags, APSR; \
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bicne arm_flags, arm_flags, #0x20000000; \
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/*orreq arm_flags, arm_flags, #0x20000000;*/ \
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msr APSR_nzcvq, arm_flags;
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#define FlagC \
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lahf; \
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@ -265,7 +282,6 @@
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#define FlagNVZC \
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lahf; \
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and arm_flags, arm_flags, #NVZC_Flags; \
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bic F_Reg, F_Reg, #NVZC_Flags; \
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orr F_Reg, F_Reg, arm_flags;
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@ -446,27 +462,29 @@
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IncOpCycles \
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9: mov EffectiveAddr, r0;
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#define bt \
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/* Virtual x86: Bit Test (carry flag only) */ \
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tst F_Reg, #C_Flag; \
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biceq r15, r15, #30; \
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orrne r15, r15, #30;
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#define btc \
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/* Virtual x86: Bit Test and Clear (carry flag only) */ \
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tst F_Reg, #C_Flag; \
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biceq r15, r15, #30;
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// ----------------------------------------------------------------------------
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// 65c02 instruction macros
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#define DoADC_b \
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GetFromEA_B \
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mov r0, r0, LSL #24; \
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mov A_Reg, A_Reg, LSL #24; \
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bt \
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mov r0, r0, LSL #24; \
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\
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/* clear ARM 'C' */ \
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adcs r1, r1, #0; \
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\
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/* set HI-C */ \
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tst F_Reg, #C_Flag; \
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adcnes A_Reg, A_Reg, #0x01000000; \
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\
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/* lahf; */ \
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/* and arm_flags, arm_flags, #VC_Flags; */ \
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/* mov arm_flags_int, arm_flags; */ \
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\
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adcs A_Reg, A_Reg, r0; \
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FlagNVZC \
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/* merge intermediate V,C */ \
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/* orr F_Reg, F_Reg, arm_flags_int; */ \
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mov A_Reg, A_Reg, LSR #24;
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#ifndef NDEBUG
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@ -491,8 +509,9 @@
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GetFromEA_B \
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mov r0, r0, LSL #24; \
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mov A_Reg, A_Reg, LSL #24; \
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ands A_Reg, r0; \
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FlagNZ
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ands A_Reg, A_Reg, r0; \
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FlagNZ \
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mov A_Reg, A_Reg, LSR #24;
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#define _DoASL(x) \
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mov x, x, LSL #24; \
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