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https://github.com/mauiaaron/apple2.git
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All 65c02 CPU tests for ARM pass, except for decimal mode
This commit is contained in:
Aaron Culliney
parent
404d4cdb4f
commit
d517339842
@ -36,8 +36,10 @@
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#ifdef __aarch64__
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# error 20150205 ARM 64bit untested!!!
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# define PTR_SHIFT #4 // 4<<1 = 8
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# define ROR_BIT 0x8000000000000000
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#else
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# define PTR_SHIFT #2 // 2<<1 = 4
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# define ROR_BIT 0x80000000
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#endif
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163
src/arm/cpu.S
163
src/arm/cpu.S
@ -358,11 +358,10 @@
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#define ea_hi_prev r1
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#define ea_hi_next r9
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#define AddIndexRegAndTestPageBoundary(IndexReg) \
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mov ea_hi_prev, r0; \
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mov ea_hi_prev, ea_hi_prev, LSR #8; \
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mov ea_hi_prev, r0, LSR #8; \
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add r0, r0, IndexReg; \
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mov ea_hi_next, r0; \
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mov ea_hi_next, ea_hi_next, LSR #8; \
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bic r0, #0x10000; \
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mov ea_hi_next, r0, LSR #8; \
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teq ea_hi_prev, ea_hi_next; \
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beq 9f;
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@ -400,15 +399,14 @@
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zero contains the high order byte of the address. */
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#define GetIndZPage \
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GetFromPC_B \
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add r0, r0, #1; \
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and r0, r0, #0xFF; \
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mov EffectiveAddr, r0; \
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GetFromEA_B \
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mov r9, r0, LSL #8; \
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sub EffectiveAddr, EffectiveAddr, #1; \
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and EffectiveAddr, EffectiveAddr, #0xFF; \
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mov r12, r0; \
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add EffectiveAddr, EffectiveAddr, #1; \
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bic EffectiveAddr, #0x100; \
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GetFromEA_B \
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orr r0, r9, r0; \
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mov r0, r0, LSL #8; \
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orr r0, r12, r0; \
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mov EffectiveAddr, r0;
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/* Zero Page Indexed Indirect Addressing - The second byte is added to
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@ -420,16 +418,16 @@
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and low-order bytes must be in page zero. */
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#define GetIndZPage_X \
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GetFromPC_B \
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add r0, r0, X_Reg; \
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add r0, r0, #1; \
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and r0, r0, #0xFF; \
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mov EffectiveAddr, r0; \
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add EffectiveAddr, EffectiveAddr, X_Reg; \
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bic EffectiveAddr, #0x100; \
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GetFromEA_B \
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mov r9, r0, LSL #8; \
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sub EffectiveAddr, EffectiveAddr, #1; \
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and EffectiveAddr, EffectiveAddr, #0xFF; \
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mov r12, r0; \
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add EffectiveAddr, EffectiveAddr, #1; \
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bic EffectiveAddr, #0x100; \
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GetFromEA_B \
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orr r0, r9, r0; \
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mov r0, r0, LSL #8; \
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orr r0, r12, r0; \
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mov EffectiveAddr, r0;
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/* Indirect Indexed Addressing - The second byte of the instruction
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@ -441,15 +439,14 @@
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effective address. */
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#define _GetIndZPage_Y \
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GetFromPC_B \
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add r0, r0, #1; \
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and r0, r0, #0xFF; \
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mov EffectiveAddr, r0; \
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GetFromEA_B \
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mov r9, r0, LSL #8; \
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sub EffectiveAddr, EffectiveAddr, #1; \
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and EffectiveAddr, EffectiveAddr, #0xFF; \
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mov r12, r0; \
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add EffectiveAddr, EffectiveAddr, #1; \
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bic EffectiveAddr, #0x100; \
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GetFromEA_B \
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orr r0, r9, r0; \
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mov r0, r0, LSL #8; \
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orr r0, r12, r0; \
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AddIndexRegAndTestPageBoundary(Y_Reg)
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#define GetIndZPage_Y \
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@ -459,12 +456,14 @@
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#define GetIndZPage_Y_STA \
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_GetIndZPage_Y \
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IncOpCycles \
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/*IncOpCycles*/ \
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9: mov EffectiveAddr, r0;
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// ----------------------------------------------------------------------------
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// 65c02 instruction macros
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#if 0
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#error this attempts to leverage ARM 32bit flags, but does so incorrectly ... possibly there is some efficiency gains here if correctness can be assured
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#define DoADC_b \
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GetFromEA_B \
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mov A_Reg, A_Reg, LSL #24; \
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@ -486,6 +485,36 @@
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/* merge intermediate V,C */ \
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/* orr F_Reg, F_Reg, arm_flags_int; */ \
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mov A_Reg, A_Reg, LSR #24;
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#else
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#define sign_a r1
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#define sign_0 r9
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#define DoADC_b \
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GetFromEA_B \
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/* save operand sign bits */ \
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mov sign_a, A_Reg, LSR #7; \
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mov sign_0, r0, LSR #7; \
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/* perform ADC with incoming carry */\
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tst F_Reg, #C_Flag; \
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addne A_Reg, A_Reg, #1; \
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add A_Reg, A_Reg, r0; \
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/* clear and set flags */ \
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bic F_Reg, F_Reg, #NVZC_Flags; \
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tst A_Reg, #0x100; \
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orrne F_Reg, F_Reg, #C_Flag; \
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bic A_Reg, #0x100; \
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\
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tst A_Reg, #0x80; \
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orrne F_Reg, F_Reg, #N_Flag; \
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\
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teq sign_a, sign_0; \
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bne 1f; \
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mov sign_0, A_Reg, LSR #7; \
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cmp sign_a, sign_0; \
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orrne F_Reg, F_Reg, #V_Flag; \
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\
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1: tst A_Reg, #0xFF; \
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orreq F_Reg, F_Reg, #Z_Flag;
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#endif
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#ifndef NDEBUG
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#define DebugBCDCheck \
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@ -526,13 +555,18 @@
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#define _DoBIT \
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GetFromEA_B \
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mov r0, r0, LSL #24; \
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mov r1, A_Reg, LSL #24; \
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tst r1, r0;
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mov r1, A_Reg; \
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and r1, r1, r0;
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#define DoBIT \
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_DoBIT \
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FlagNVZ
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bic F_Reg, F_Reg, #NVZ_Flags; \
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tst r1, #0xFF; \
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orreq F_Reg, F_Reg, #Z_Flag; \
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tst r0, #0x40; \
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orrne F_Reg, F_Reg, #V_Flag; \
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tst r0, #0x80; \
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orrne F_Reg, F_Reg, #N_Flag;
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#define DoCMP \
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GetFromEA_B \
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@ -634,7 +668,7 @@
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#define _DoPLx(x) \
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Pop(x); \
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mov r0, x, LSL #24; \
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orr r0, r0, r0; \
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orrs r0, r0, r0; \
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FlagNZ
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#define _DoROL(x) \
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@ -654,20 +688,59 @@
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#define _DoROR(x) \
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tst F_Reg, #C_Flag; \
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orrne x, x, #0x100; \
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rors x, x, #1; \
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FlagNZC
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ror x, x, #1; \
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bic F_Reg, F_Reg, #NZC_Flags; \
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tst x, #ROR_BIT; \
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bicne x, #ROR_BIT; \
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orrne F_Reg, F_Reg, #C_Flag; \
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tst x, #0xFF; \
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orreq F_Reg, F_Reg, #Z_Flag; \
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tst x, #0x80; \
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orrne F_Reg, F_Reg, #N_Flag;
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#define DoROR \
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GetFromEA_B \
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_DoROR(r0) \
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PutToEA_B
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#if 0
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#error this attempts to leverage ARM 32bit flags, but does so incorrectly ... possibly there is some efficiency gains here if correctness can be assured
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#define DoSBC_b \
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GetFromEA_B \
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mvn r0, r0; \
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adcs r1, r1, #0; \
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bt; \
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adcs A_Reg, A_Reg, r0; \
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FlagNVZC
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#else
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#define DoSBC_b \
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GetFromEA_B \
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/* save operand sign bits */ \
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mov sign_a, A_Reg, LSR #7; \
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mov sign_0, r0, LSR #7; \
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/* perform SBC with incoming borrow */\
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sub A_Reg, A_Reg, r0; \
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tst F_Reg, #C_Flag; \
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subeq A_Reg, A_Reg, #1; \
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/* clear and set flags */ \
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bic F_Reg, F_Reg, #NVZC_Flags; \
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tst A_Reg, #0x80000000; \
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orreq F_Reg, F_Reg, #C_Flag; \
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mov A_Reg, A_Reg, LSL #24; \
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mov A_Reg, A_Reg, LSR #24; \
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\
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tst A_Reg, #0x80; \
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orrne F_Reg, F_Reg, #N_Flag; \
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\
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teq sign_a, sign_0; \
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beq 1f; \
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mov sign_0, A_Reg, LSR #7; \
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cmp sign_a, sign_0; \
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orrne F_Reg, F_Reg, #V_Flag; \
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\
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1: tst A_Reg, #0xFF; \
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orreq F_Reg, F_Reg, #Z_Flag;
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#endif
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#define DoSTA \
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mov r0, A_Reg; \
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@ -687,7 +760,7 @@
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#define DoTRB \
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GetFromEA_B \
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teq r0, A_Reg; \
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tst r0, A_Reg; \
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FlagZ \
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mvn r1, A_Reg; \
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and r0, r0, r1; \
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@ -695,7 +768,7 @@
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#define DoTSB \
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GetFromEA_B \
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teq r0, A_Reg; \
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tst r0, A_Reg; \
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FlagZ \
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orr r0, A_Reg, r0; \
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PutToEA_B
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@ -1054,7 +1127,9 @@ ENTRY(op_BIT_abs_x)
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ENTRY(op_BIT_imm)
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GetImm
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_DoBIT
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FlagZ
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tst r1, #0xFF
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orreq F_Reg, F_Reg, #Z_Flag
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bicne F_Reg, F_Reg, #Z_Flag
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Continue
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.ltorg
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@ -1464,18 +1539,21 @@ ENTRY(op_JMP_abs)
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ENTRY(op_JMP_ind) // 0x6c
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GetFromPC_W
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and r1, r0, #0xFF
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eor r1, #0xFF
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mov r1, r0, LSL #24
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teq r1, #0xFF000000
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beq jmp_special
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GetFromMem_W(r0)
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mov PC_Reg, r0
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Continue
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jmp_special: // see JMP indirect note in _Understanding the Apple IIe_ 4-25
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mov PC_Reg, r0
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sub PC_Reg, #0xFF
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subs PC_Reg, PC_Reg, #0xFF
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movmi PC_Reg, PC_Reg, LSL #16
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movmi PC_Reg, PC_Reg, LSR #16
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GetFromMem_B(PC_Reg)
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mov r9, r0, LSL #8
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add PC_Reg, #0xFF
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add PC_Reg, PC_Reg, #0xFF
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bic PC_Reg, #0x10000
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GetFromMem_B(PC_Reg)
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orr r0, r9, r0
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mov PC_Reg, r0
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@ -1486,10 +1564,11 @@ ENTRY(op_JMP_abs_ind_x)
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GetFromPC_W
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mov EffectiveAddr, r0
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mov r0, X_Reg
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cbw
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add EffectiveAddr, r0
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mov EffectiveAddr, EffectiveAddr, LSL #24 // 16bit under/overflow protection
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mov EffectiveAddr, EffectiveAddr, LSR #24
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#warning HACK FIXME TODO : need to check the Bible here ... is this a signed addition (in which case we need to cbw)
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//cbw
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add EffectiveAddr, EffectiveAddr, r0
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mov EffectiveAddr, EffectiveAddr, LSL #16 // 16bit under/overflow protection
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mov EffectiveAddr, EffectiveAddr, LSR #16
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GetFromMem_W(EffectiveAddr)
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mov PC_Reg, r0
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Continue
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@ -15,16 +15,16 @@
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#define GLUE_BANK_MAYBEREAD(func,pointer) \
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ENTRY(func) ldr r1, SYM(softswitches); \
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ldr r0, [r1]; \
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ldr r1, SYM(pointer); \
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tst r0, $SS_CXROM; \
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beq 1f; \
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ldr r1, SYM(pointer); \
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ldr r1, [r1]; \
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ldrb r0, [r1, EffectiveAddr]; \
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mov pc, lr; \
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1: ldr r1, SYM(pointer); \
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push {lr}; \
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1: push {lr}; \
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blx r1; \
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pop {pc}; \
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pop {pc};
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#warning FIXME TODO ^^^^^^^^^^^^^ this CXROM codepath is quite likely buggy since this stuff is unimplemented =)
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#define GLUE_BANK_READ(func,pointer) \
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ENTRY(func) ldr r1, SYM(pointer); \
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@ -47,18 +47,18 @@ ENTRY(func) ldr r1, SYM(pointer); \
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#define GLUE_C_WRITE(func) \
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ENTRY(func) push {r0, PC_Reg, SP_Reg, F_Reg, Y_Reg, X_Reg, A_Reg, lr}; \
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and r0, #0xff; \
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ENTRY(func) push {r0, EffectiveAddr, PC_Reg, SP_Reg, F_Reg, Y_Reg, X_Reg, A_Reg, lr}; \
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and r0, r0, #0xff; \
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mov r1, r0; \
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mov r0, EffectiveAddr; \
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bl CALL(c_##func); \
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pop {r0, PC_Reg, SP_Reg, F_Reg, Y_Reg, X_Reg, A_Reg, pc};
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pop {r0, EffectiveAddr, PC_Reg, SP_Reg, F_Reg, Y_Reg, X_Reg, A_Reg, pc};
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#define GLUE_C_READ(func) \
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ENTRY(func) push {PC_Reg, SP_Reg, F_Reg, Y_Reg, X_Reg, A_Reg, lr}; \
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ENTRY(func) push {EffectiveAddr, PC_Reg, SP_Reg, F_Reg, Y_Reg, X_Reg, A_Reg, lr}; \
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mov r0, EffectiveAddr; \
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bl CALL(c_##func); \
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pop {PC_Reg, SP_Reg, F_Reg, Y_Reg, X_Reg, A_Reg, pc};
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pop {EffectiveAddr, PC_Reg, SP_Reg, F_Reg, Y_Reg, X_Reg, A_Reg, pc};
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#define GLUE_C_READ_ALTZP(FUNC) GLUE_C_READ(FUNC)
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@ -1268,10 +1268,10 @@ ENTRY(op_JMP_ind) // 0x6c
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Continue
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jmp_special: // see JMP indirect note in _Understanding the Apple IIe_ 4-25
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movw %ax, PC_Reg
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subw $0xff, PC_Reg
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subw $0xFF, PC_Reg
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GetFromMem_B(PC_Reg_X)
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xchgb %al, %ah
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addw $0xff, PC_Reg
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addw $0xFF, PC_Reg
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GetFromMem_B(PC_Reg_X)
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movw %ax, PC_Reg
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Continue
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@ -1281,6 +1281,8 @@ ENTRY(op_JMP_abs_ind_x)
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GetFromPC_W
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movw %ax, EffectiveAddr
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movzbLQ X_Reg, _XAX
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#warning HACK FIXME TODO : need to check the Bible here ... is this a signed addition (in which case we need to cbw)
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//cbw
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addw %ax, EffectiveAddr
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GetFromMem_W(EffectiveAddr_X)
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movw %ax, PC_Reg
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