/* This file is auto-generated for a specific architecture ABI */
#define CPU_IRQCHECK 0
#define CPU65_TRACE_PROLOGUE 4
#define CPU65_TRACE_ARG 8
#define CPU65_TRACE_ARG1 12
#define CPU65_TRACE_ARG2 16
#define CPU65_TRACE_EPILOGUE 20
#define CPU65_TRACE_IRQ 24
#define DEBUG_ILLEGAL_BCD 28
#define CPU65_VMEM_R 32
#define CPU65_VMEM_W 36
#define CPU65_FLAGS_ENCODE 40
#define CPU65_FLAGS_DECODE 44
#define CPU65__OPCODES 48
#define CPU65__OPCYCLES 52
#define BASE_RAMRD 56
#define BASE_RAMWRT 60
#define BASE_TEXTRD 64
#define BASE_TEXTWRT 68
#define BASE_HGRRD 72
#define BASE_HGRWRT 76
#define BASE_STACKZP 80
#define BASE_D000_RD 84
#define BASE_E000_RD 88
#define BASE_D000_WRT 92
#define BASE_E000_WRT 96
#define BASE_C3ROM 100
#define BASE_C4ROM 104
#define BASE_C5ROM 108
#define BASE_CXROM 112
#define SOFTSWITCHES 116
#define GC_CYCLES_TIMER_0 120
#define GC_CYCLES_TIMER_1 124
#define CPU65_CYCLES_TO_EXECUTE 128
#define CPU65_CYCLE_COUNT 132
#define IRQ_CHECK_TIMEOUT 136
#define INTERRUPT_VECTOR 140
#define RESET_VECTOR 142
#define CPU65_PC 144
#define CPU65_EA 146
#define CPU65_A 148
#define CPU65_F 149
#define CPU65_X 150
#define CPU65_Y 151
#define CPU65_SP 152
#define CPU65_D 153
#define CPU65_RW 154
#define CPU65_OPCODE 155
#define CPU65_OPCYCLES 156
#define CPU65__SIGNAL 157
#define JOY_BUTTON0 158
#define JOY_BUTTON1 159
#define EMUL_REINITIALIZE 160