/* This file is auto-generated for a specific architecture ABI */
#define CPU_IRQCHECK 0
#define CPU65_TRACE_PROLOGUE 8
#define CPU65_TRACE_ARG 16
#define CPU65_TRACE_ARG1 24
#define CPU65_TRACE_ARG2 32
#define CPU65_TRACE_EPILOGUE 40
#define CPU65_TRACE_IRQ 48
#define DEBUG_ILLEGAL_BCD 56
#define CPU65_VMEM_R 64
#define CPU65_VMEM_W 72
#define CPU65_FLAGS_ENCODE 80
#define CPU65_FLAGS_DECODE 88
#define CPU65__OPCODES 96
#define CPU65__OPCYCLES 104
#define BASE_RAMRD 112
#define BASE_RAMWRT 120
#define BASE_TEXTRD 128
#define BASE_TEXTWRT 136
#define BASE_HGRRD 144
#define BASE_HGRWRT 152
#define BASE_STACKZP 160
#define BASE_D000_RD 168
#define BASE_E000_RD 176
#define BASE_D000_WRT 184
#define BASE_E000_WRT 192
#define BASE_C3ROM 200
#define BASE_C4ROM 208
#define BASE_C5ROM 216
#define BASE_CXROM 224
#define SOFTSWITCHES 232
#define GC_CYCLES_TIMER_0 236
#define GC_CYCLES_TIMER_1 240
#define CPU65_CYCLES_TO_EXECUTE 244
#define CPU65_CYCLE_COUNT 248
#define IRQ_CHECK_TIMEOUT 252
#define INTERRUPT_VECTOR 256
#define RESET_VECTOR 258
#define CPU65_PC 260
#define CPU65_EA 262
#define CPU65_A 264
#define CPU65_F 265
#define CPU65_X 266
#define CPU65_Y 267
#define CPU65_SP 268
#define CPU65_D 269
#define CPU65_RW 270
#define CPU65_OPCODE 271
#define CPU65_OPCYCLES 272
#define CPU65__SIGNAL 273
#define JOY_BUTTON0 274
#define JOY_BUTTON1 275
#define EMUL_REINITIALIZE 276