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54 lines
1.3 KiB
C
54 lines
1.3 KiB
C
/* This file is auto-generated for a specific architecture ABI */
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#define UNUSED0 0
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#define CPU65_TRACE_PROLOGUE 8
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#define CPU65_TRACE_ARG 16
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#define UNUSED1 24
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#define UNUSED2 32
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#define CPU65_TRACE_EPILOGUE 40
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#define CPU65_TRACE_IRQ 48
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#define DEBUG_ILLEGAL_BCD 56
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#define CPU65_VMEM_R 64
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#define CPU65_VMEM_W 72
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#define CPU65_FLAGS_ENCODE 80
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#define CPU65_FLAGS_DECODE 88
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#define CPU65__OPCODES 96
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#define CPU65__OPCYCLES 104
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#define BASE_RAMRD 112
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#define BASE_RAMWRT 120
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#define BASE_TEXTRD 128
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#define BASE_TEXTWRT 136
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#define BASE_HGRRD 144
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#define BASE_HGRWRT 152
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#define BASE_STACKZP 160
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#define BASE_D000_RD 168
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#define BASE_E000_RD 176
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#define BASE_D000_WRT 184
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#define BASE_E000_WRT 192
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#define BASE_C3ROM 200
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#define BASE_C4ROM 208
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#define BASE_C5ROM 216
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#define BASE_CXROM 224
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#define SOFTSWITCHES 232
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#define GC_CYCLES_TIMER_0 236
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#define GC_CYCLES_TIMER_1 240
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#define CPU65_CYCLES_TO_EXECUTE 244
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#define CPU65_CYCLE_COUNT 248
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#define UNUSED3 252
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#define INTERRUPT_VECTOR 256
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#define RESET_VECTOR 258
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#define CPU65_PC 260
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#define CPU65_EA 262
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#define CPU65_A 264
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#define CPU65_F 265
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#define CPU65_X 266
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#define CPU65_Y 267
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#define CPU65_SP 268
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#define CPU65_D 269
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#define CPU65_RW 270
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#define CPU65_OPCODE 271
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#define CPU65_OPCYCLES 272
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#define CPU65__SIGNAL 273
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#define JOY_BUTTON0 274
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#define JOY_BUTTON1 275
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#define EMUL_REINITIALIZE 276
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