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2 Commits
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ba617a5779
| Author | SHA1 | Date |
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Oliver Schmidt
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ba617a5779 | |
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Oliver Schmidt
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60622b9097 |
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@ -1,3 +1,3 @@
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a.out
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src/gpclk
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pidrive/*.o
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pidrive/*#062000
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pipico/build/
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@ -1,18 +1,25 @@
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set(PROJECT_NAME Apple-II-Pi)
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cmake_minimum_required(VERSION 3.12)
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include(pico_sdk_import.cmake)
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project(${PROJECT_NAME} C CXX ASM)
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pico_sdk_init()
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project(${PROJECT_NAME} C CXX ASM)
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add_executable(${PROJECT_NAME})
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pico_add_extra_outputs(${PROJECT_NAME})
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pico_enable_stdio_uart(${PROJECT_NAME} 0)
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pico_enable_stdio_usb(${PROJECT_NAME} 1)
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pico_generate_pio_header(${PROJECT_NAME} ${CMAKE_CURRENT_LIST_DIR}/bus.pio)
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include(FetchContent)
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FetchContent_Declare(a2pico
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GIT_REPOSITORY https://github.com/oliverschmidt/a2pico.git
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GIT_TAG main
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)
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FetchContent_MakeAvailable(a2pico)
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add_dependencies(${PROJECT_NAME} rom)
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add_custom_target(rom make -C ../../pidrive)
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target_sources(${PROJECT_NAME} PRIVATE
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main.c
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@ -23,5 +30,5 @@ target_sources(${PROJECT_NAME} PRIVATE
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target_link_libraries(${PROJECT_NAME} PRIVATE
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pico_stdlib
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pico_multicore
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hardware_pio
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a2pico
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)
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@ -24,7 +24,7 @@ SOFTWARE.
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*/
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#include "bus.pio.h"
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#include <a2pico.h>
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#include "board.h"
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@ -32,71 +32,53 @@ extern const __attribute__((aligned(4))) uint8_t firmware[];
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static bool active;
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static void __time_critical_func(callback)(uint gpio, uint32_t events) {
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if (events & GPIO_IRQ_EDGE_FALL) {
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active = false;
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}
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}
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static uint32_t command;
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static uint32_t control;
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void __time_critical_func(board)(void) {
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for (uint gpio = gpio_addr; gpio < gpio_addr + size_addr; gpio++) {
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gpio_init(gpio);
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gpio_set_pulls(gpio, false, false); // floating
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}
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for (uint gpio = gpio_data; gpio < gpio_data + size_data; gpio++) {
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pio_gpio_init(pio0, gpio);
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gpio_set_pulls(gpio, false, false); // floating
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}
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a2pico_init(pio0);
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gpio_init(gpio_enbl);
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gpio_set_pulls(gpio_enbl, false, false); // floating
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uint offset;
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offset = pio_add_program(pio0, &enbl_program);
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enbl_program_init(offset);
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offset = pio_add_program(pio0, &write_program);
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write_program_init(offset);
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offset = pio_add_program(pio0, &read_program);
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read_program_init(offset);
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active = false;
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command = 0;
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control = 0;
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a2pico_resetcallback(&callback);
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while (true) {
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uint32_t enbl = pio_sm_get_blocking(pio0, sm_enbl);
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uint32_t addr = enbl & 0x0FFF;
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uint32_t io = enbl & 0x0F00; // IOSTRB or IOSEL
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uint32_t strb = enbl & 0x0800; // IOSTRB
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uint32_t read = enbl & 0x1000; // R/W
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uint32_t pico = a2pico_getaddr(pio0);
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uint32_t addr = pico & 0x0FFF;
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uint32_t io = pico & 0x0F00; // IOSTRB or IOSEL
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uint32_t strb = pico & 0x0800; // IOSTRB
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uint32_t read = pico & 0x1000; // R/W
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if (read) {
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if (!io) { // DEVSEL
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switch (addr & 0xF) {
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case 0x8:
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pio_sm_put(pio0, sm_read, sio_hw->fifo_rd);
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a2pico_putdata(pio0, sio_hw->fifo_rd);
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break;
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case 0x9:
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// SIO_FIFO_ST_VLD_BITS _u(0x00000001)
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// SIO_FIFO_ST_RDY_BITS _u(0x00000002)
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pio_sm_put(pio0, sm_read, (sio_hw->fifo_st & 3) << 3);
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a2pico_putdata(pio0, (sio_hw->fifo_st & 3) << 3);
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break;
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case 0xA:
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pio_sm_put(pio0, sm_read, command);
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a2pico_putdata(pio0, command);
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break;
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case 0xB:
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pio_sm_put(pio0, sm_read, control);
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a2pico_putdata(pio0, control);
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break;
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}
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} else {
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if (!strb || (active && (addr != 0x0FFF))) {
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pio_sm_put(pio0, sm_read, firmware[addr]);
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a2pico_putdata(pio0, firmware[addr]);
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}
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}
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} else {
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uint32_t data = pio_sm_get_blocking(pio0, sm_write);
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uint32_t data = a2pico_getdata(pio0);
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if (!io) { // DEVSEL
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switch (addr & 0xF) {
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case 0x8:
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205
pipico/bus.pio
205
pipico/bus.pio
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@ -1,205 +0,0 @@
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///////////////////////////////////////////////////////////////////////////////
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/*
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MIT License
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Copyright (c) 2022 Oliver Schmidt (https://a2retro.de/)
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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*/
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///////////////////////////////////////////////////////////////////////////////
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.define public gpio_addr 2 // 12 pins
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.define public gpio_rw 14
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.define public gpio_data 15 // 8 pins
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.define public gpio_enbl 23 // DEVSEL | IOSEL | IOSTRB
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.define public gpio_irq 24
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.define public gpio_res 25
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.define public size_addr 13 // incl. R/W
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.define public size_data 8
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.define public sm_enbl 0
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.define public sm_read 1 // from Apple II perspective
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.define public sm_write 2 // from Apple II perspective
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.define irq_write 4
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/*
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Implementation of the Apple II peripheral bus protocol:
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- /DEVSEL, /IOSEL and /IOSTRB are supposed to combined to ENBL via an AND gate.
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- On the falling edge of ENBL, the lines A0-A11 and R/W are sampled and pushed
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into the 'enable' state machine RX FIFO.
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- In case of an Apple II write cycle, the lines D0-D7 are sampled ~300ns later
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and pushed into the 'write' state machine RX FIFO.
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- If a byte is pushed into the 'read' state machine TX FIFO, it is driven out
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to the lines D0-D7 until the rising edge of ENBL.
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*/
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///////////////////////////////////////////////////////////////////////////////
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.program enbl
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.wrap_target
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idle:
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wait 1 gpio gpio_enbl // wait for ENBL to rise
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wait 0 gpio gpio_enbl // wait for ENBL to fall
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in pins, size_addr // shift A0-A11 + R/W into ISR
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jmp pin idle // jump to 'idle' if R/W is high
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irq irq_write // set 'write' IRQ
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.wrap
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% c-sdk {
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static inline void enbl_program_init(uint offset) {
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pio_sm_config c = enbl_program_get_default_config(offset);
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// in_base: gpio_addr
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sm_config_set_in_pins(&c, gpio_addr);
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// shift_right: false
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// autopush: true
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// push_threshold: size_addr
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sm_config_set_in_shift(&c, false, true, size_addr);
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// pin: gpio_rw
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sm_config_set_jmp_pin(&c, gpio_rw);
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// state_machine: sm_enbl
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// initial_pc: offset
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pio_sm_init(pio0, sm_enbl, offset, &c);
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// state_machine: sm_enbl
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pio_sm_set_enabled(pio0, sm_enbl, true);
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}
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%}
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///////////////////////////////////////////////////////////////////////////////
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.program write
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.wrap_target
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wait 1 irq irq_write [31] // wait for 'write' IRQ to be set and clear it
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// [31 cycles to allow 6502 to set up D0-D7]
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in pins, size_data // shift D0-D7 into ISR
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.wrap
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% c-sdk {
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static inline void write_program_init(uint offset) {
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pio_sm_config c = write_program_get_default_config(offset);
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// in_base: gpio_data
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sm_config_set_in_pins(&c, gpio_data);
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// shift_right: false
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// autopush: true
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// push_threshold: size_data
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sm_config_set_in_shift(&c, false, true, size_data);
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// state_machine: sm_write
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// initial_pc: offset
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pio_sm_init(pio0, sm_write, offset, &c);
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// state_machine: sm_write
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pio_sm_set_enabled(pio0, sm_write, true);
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}
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%}
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///////////////////////////////////////////////////////////////////////////////
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.program read
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/*
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Both set and set-side are limited to 5 pins each. So both set and side-set are
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configured to set (the direction of) 4 pins. This approach allows to set the
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direction of D0-D7 in one operation.
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Note: The naive approach would have been
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mov osr, ~x // move 0xFFFFFFFF to OSR
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out pindirs, size_data // enable output of D0-D7
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[...]
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mov osr, x // move 0x00000000 to OSR
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out pindirs, size_data // disable output of D0-D7
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but this would have required two operations and destroyed OSR.
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*/
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.side_set (size_data / 2) opt pindirs
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.wrap_target
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pull block // pull data into OSR, block on empty FIFO
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out pins, size_data // shift OSR out to D0-D7
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set pindirs, 15 side 15 // enable output of D0-D7
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wait 1 gpio gpio_enbl // wait for ENBL to rise
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set pindirs, 0 side 0 // disable output of D0-D7
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.wrap
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% c-sdk {
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static inline void read_program_init(uint offset) {
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pio_sm_config c = read_program_get_default_config(offset);
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// out_base: gpio_data
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// out_count: size_data
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sm_config_set_out_pins(&c, gpio_data, size_data);
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// shift_right: true
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// autopull: false
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// pull_threshold: size_data
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sm_config_set_out_shift(&c, true, false, size_data);
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// set_base: gpio_data
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// set_count: size_data / 2
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sm_config_set_set_pins(&c, gpio_data, size_data / 2);
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// sideset_base: gpio_data + size_data / 2
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sm_config_set_sideset_pins(&c, gpio_data + size_data / 2);
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// state_machine: sm_read
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// initial_pc: offset
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pio_sm_init(pio0, sm_read, offset, &c);
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// state_machine: sm_read
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pio_sm_set_enabled(pio0, sm_read, true);
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}
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%}
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///////////////////////////////////////////////////////////////////////////////
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@ -29,7 +29,6 @@ SOFTWARE.
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#include <pico/stdlib.h>
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#include <pico/multicore.h>
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#include "bus.pio.h"
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#include "board.h"
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#ifdef TRACE
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@ -49,17 +48,14 @@ void uart_printf(uart_inst_t *uart, const char *format, ...) {
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void main(void) {
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multicore_launch_core1(board);
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gpio_init(gpio_irq);
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gpio_pull_up(gpio_irq);
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stdio_init_all();
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stdio_set_translate_crlf(&stdio_usb, false);
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#ifdef TRACE
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uart_init(uart0, 115200);
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uart_set_translate_crlf(uart0, true);
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gpio_set_function(0, GPIO_FUNC_UART);
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gpio_set_function(1, GPIO_FUNC_UART);
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gpio_set_function(PICO_DEFAULT_UART_TX_PIN, GPIO_FUNC_UART);
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gpio_set_function(PICO_DEFAULT_UART_RX_PIN, GPIO_FUNC_UART);
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#endif
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while (true) {
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