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worked out why STA seemed an exception
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@ -17,43 +17,28 @@ given on http://www.6502.org/tutorials/6502opcodes.html )
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NOTE: there appears to be an error in AND and ORA zero page timings on that
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NOTE: there appears to be an error in AND and ORA zero page timings on that
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webpage given above. I've now corrected this below.
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webpage given above. I've now corrected this below.
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There are 11 classes of instructions when it comes to cycle times:
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There are 10 classes of instructions when it comes to cycle times:
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Class Ia
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Class I
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(followed by ADC, AND, BIT, CMP, CPX, CPY, EOR, LDA, LDX, LDY, ORA, SBC, STX,
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(followed by ADC, AND, BIT, CMP, CPX, CPY, EOR, LDA, LDX, LDY, ORA, SBC, STA,
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STY)
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STX, STY)
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immediate 2
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immediate 2
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zero page 3
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zero page 3
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zero page, x 4
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zero page, x 4
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zero page, y 4
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zero page, y 4
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absolute 4
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absolute 4
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absolute, x 4 (+1 if page crossed)
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absolute, x 4 (+1 if page crossed or writing)
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absolute, y 4 (+1 if page crossed)
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absolute, y 4 (+1 if page crossed or writing)
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indirect, x 6
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indirect, x 6
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indirect, y 5 (+1 if page crossed)
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indirect, y 5 (+1 if page crossed or writing)
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Note 1: the zero page indexed and x-index indirect don't have the page cross
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Note 1: the zero page indexed and x-index indirect don't have the page cross
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addition because they wrap.
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addition because they wrap.
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Note 2: writes to indexed non-zero-page memory (e.g. STA) have the +1 even
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Class Ib
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if not page crossing.
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(followed by STA)
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zero page 3
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zero page, x 4
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zero page, y 4
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absolute 4
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absolute, x 5
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absolute, y 5
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indirect, x 6
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indirect, y 6
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Note 2: just like Class Ia BUT takes the cycles it would take if there's a
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page cross even if there isn't.
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Question 1: why is this?
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Class II
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Class II
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@ -65,10 +50,8 @@ zero page, x 6
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absolute 6
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absolute 6
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absolute, x 7
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absolute, x 7
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Note 4: looks like class Ib + 2 in the non-implied cases
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Note 3: looks like class I +2 (with the absolute, x +1 even if not page
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crossing)
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Question 2: why does absolute, x not have a page crossing addition? same
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reason as for Ib?
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Class IIIa
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Class IIIa
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