start splitting for https://github.com/jtauber/applepy/issues/18
This commit is contained in:
JensDiemer
parent
fe80bc897d
commit
82dcec24b6
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@ -0,0 +1,16 @@
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from generic.generic_config import BaseConfig
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class Apple2Config(BaseConfig):
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ROM_START = 0xD000
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ROM_SIZE = 0x3000
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ROM_END = ROM_START + ROM_SIZE # 0x10000
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RAM_START = 0x0000
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RAM_SIZE = 0xC000
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RAM_END = RAM_START + RAM_SIZE # 0xc000
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if __name__ == "__main__":
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cfg = Apple2Config()
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cfg.print_debug_info()
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@ -0,0 +1,21 @@
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from generic.base_memory import MemoryBase, ROMBase, RAMBase
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class ROM(ROMBase):
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pass
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class RAM(RAMBase):
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pass
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class Memory(MemoryBase):
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def read_word_bug(self, cycle, address):
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if address % 0x100 == 0xFF:
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return self.read_byte(cycle, address) + (self.read_byte(cycle + 1, address & 0xFF00) << 8)
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else:
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return self.read_word(cycle, address)
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def write_byte(self, cycle, address, value):
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if address < self.cfg.RAM_SIZE:
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self.ram.write_byte(address, value)
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if 0x400 <= address < 0x800 or 0x2000 <= address < 0x5FFF:
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self.bus_write(cycle, address, value)
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19
applepy.py
19
applepy.py
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@ -15,6 +15,8 @@ import sys
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import time
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import wave
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from apple2.apple2config import Apple2Config
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class Display:
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@ -364,19 +366,23 @@ class SoftSwitches:
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class Apple2:
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def __init__(self, options, display, speaker, cassette):
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def __init__(self, cfg, options, display, speaker, cassette):
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self.cfg = cfg
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self.display = display
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self.speaker = speaker
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self.softswitches = SoftSwitches(display, speaker, cassette)
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listener = socket.socket()
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listener.bind(("127.0.0.1", 0))
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listener.bind((self.cfg.LOCAL_HOST_IP, 0))
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listener.listen(0)
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bus_port = listener.getsockname()[1]
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print "bus I/O listen on %s:%s" % (self.cfg.LOCAL_HOST_IP, bus_port)
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args = [
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sys.executable,
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"cpu6502.py",
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"--bus", str(listener.getsockname()[1]),
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"--bus", str(bus_port),
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"--rom", options.rom,
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]
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if options.ram:
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@ -391,11 +397,12 @@ class Apple2:
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rs, _, _ = select.select([listener], [], [], 2)
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if not rs:
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print >>sys.stderr, "CPU module did not start"
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print >> sys.stderr, "CPU module did not start '%s'" % " ".join(args)
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sys.exit(1)
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self.cpu, _ = listener.accept()
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def run(self):
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sys.stdout.flush()
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update_cycle = 0
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quit = False
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while not quit:
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@ -485,10 +492,12 @@ def get_options():
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if __name__ == "__main__":
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cfg = Apple2Config()
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options = get_options()
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display = Display()
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speaker = None if options.quiet else Speaker()
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cassette = Cassette(options.cassette) if options.cassette else None
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apple = Apple2(options, display, speaker, cassette)
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apple = Apple2(cfg, options, display, speaker, cassette)
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apple.run()
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134
cpu6502.py
134
cpu6502.py
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@ -8,11 +8,10 @@ import json
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import re
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import select
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import socket
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import struct
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import sys
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bus = None # socket for bus I/O
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from apple2.apple2memory import Memory, RAM, ROM
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from apple2.apple2config import Apple2Config
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def signed(x):
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@ -21,97 +20,6 @@ def signed(x):
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return x
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class ROM:
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def __init__(self, start, size):
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self.start = start
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self.end = start + size - 1
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self._mem = [0x00] * size
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def load(self, address, data):
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for offset, datum in enumerate(data):
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self._mem[address - self.start + offset] = datum
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def load_file(self, address, filename):
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with open(filename, "rb") as f:
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for offset, datum in enumerate(f.read()):
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self._mem[address - self.start + offset] = ord(datum)
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def read_byte(self, address):
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assert self.start <= address <= self.end
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return self._mem[address - self.start]
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class RAM(ROM):
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def write_byte(self, address, value):
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self._mem[address] = value
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class Memory:
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def __init__(self, options=None, use_bus=True):
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self.use_bus = use_bus
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self.rom = ROM(0xD000, 0x3000)
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if options:
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self.rom.load_file(0xD000, options.rom)
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self.ram = RAM(0x0000, 0xC000)
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if options and options.ram:
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self.ram.load_file(0x0000, options.ram)
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def load(self, address, data):
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if address < 0xC000:
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self.ram.load(address, data)
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def read_byte(self, cycle, address):
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if address < 0xC000:
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return self.ram.read_byte(address)
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elif address < 0xD000:
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return self.bus_read(cycle, address)
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else:
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return self.rom.read_byte(address)
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def read_word(self, cycle, address):
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return self.read_byte(cycle, address) + (self.read_byte(cycle + 1, address + 1) << 8)
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def read_word_bug(self, cycle, address):
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if address % 0x100 == 0xFF:
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return self.read_byte(cycle, address) + (self.read_byte(cycle + 1, address & 0xFF00) << 8)
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else:
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return self.read_word(cycle, address)
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def write_byte(self, cycle, address, value):
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if address < 0xC000:
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self.ram.write_byte(address, value)
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if 0x400 <= address < 0x800 or 0x2000 <= address < 0x5FFF:
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self.bus_write(cycle, address, value)
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def bus_read(self, cycle, address):
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if not self.use_bus:
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return 0
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op = struct.pack("<IBHB", cycle, 0, address, 0)
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try:
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bus.send(op)
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b = bus.recv(1)
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if len(b) == 0:
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sys.exit(0)
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return ord(b)
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except socket.error:
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sys.exit(0)
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def bus_write(self, cycle, address, value):
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if not self.use_bus:
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return
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op = struct.pack("<IBHB", cycle, 1, address, value)
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try:
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bus.send(op)
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except IOError:
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sys.exit(0)
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class Disassemble:
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def __init__(self, cpu, memory):
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self.cpu = cpu
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@ -504,12 +412,16 @@ class CPU:
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STACK_PAGE = 0x100
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RESET_VECTOR = 0xFFFC
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def __init__(self, options, memory):
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def __init__(self, cfg, bus, options, memory):
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self.cfg = cfg
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self.bus = bus
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self.memory = memory
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self.control_server = BaseHTTPServer.HTTPServer(("127.0.0.1", 6502), ControlHandlerFactory(self))
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self.control_server = BaseHTTPServer.HTTPServer(
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(self.cfg.LOCAL_HOST_IP, 6502), ControlHandlerFactory(self)
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)
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self.accumulator = 0x00
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self.x_index = 0x00
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self.y_index = 0x00
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@ -689,12 +601,9 @@ class CPU:
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def reset(self):
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self.program_counter = self.read_word(self.RESET_VECTOR)
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def run(self, bus_port):
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global bus
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bus = socket.socket()
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bus.connect(("127.0.0.1", bus_port))
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def run(self):
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sys.stdout.flush()
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while not self.quit:
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timeout = 0
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@ -1198,7 +1107,7 @@ def get_options():
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if sys.argv[a].startswith("-"):
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if sys.argv[a] in ("-b", "--bus"):
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a += 1
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options.bus = int(sys.argv[a])
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options.bus_port = int(sys.argv[a])
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elif sys.argv[a] in ("-p", "--pc"):
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a += 1
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options.pc = int(sys.argv[a])
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@ -1219,12 +1128,19 @@ def get_options():
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if __name__ == "__main__":
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options = get_options()
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if options.bus is None:
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if options.bus_port is None:
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print "ApplePy cpu core"
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print "Run applepy.py instead"
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sys.exit(0)
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mem = Memory(options)
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cpu = CPU(options, mem)
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cpu.run(options.bus)
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cfg = Apple2Config()
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bus = socket.socket()
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bus_address = (cfg.LOCAL_HOST_IP, options.bus_port)
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print "bus I/O connect to %s" % repr(bus_address)
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bus.connect(bus_address)
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mem = Memory(cfg, bus, RAM, ROM, options)
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cpu = CPU(cfg, bus, options, mem)
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cpu.run()
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@ -0,0 +1,84 @@
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import sys
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import socket
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import struct
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class ROMBase(object):
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def __init__(self, start, size):
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self.start = start
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self.end = start + size - 1
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self._mem = [0x00] * size
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def load(self, address, data):
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for offset, datum in enumerate(data):
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self._mem[address - self.start + offset] = datum
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def load_file(self, address, filename):
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with open(filename, "rb") as f:
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for offset, datum in enumerate(f.read()):
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self._mem[address - self.start + offset] = ord(datum)
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def read_byte(self, address):
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assert self.start <= address <= self.end
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return self._mem[address - self.start]
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class RAMBase(ROMBase):
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def write_byte(self, address, value):
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self._mem[address] = value
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class MemoryBase(object):
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def __init__(self, cfg, bus, ram_class, rom_class, options=None, use_bus=True):
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self.cfg = cfg
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if use_bus:
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self.bus = bus
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self.use_bus = use_bus
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self.rom = rom_class(self.cfg.ROM_START, self.cfg.ROM_SIZE)
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if options:
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self.rom.load_file(self.cfg.ROM_START, options.rom)
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self.ram = ram_class(self.cfg.RAM_START, self.cfg.RAM_SIZE)
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if options and options.ram:
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self.ram.load_file(self.cfg.RAM_START, options.ram)
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def load(self, address, data):
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if address < self.cfg.RAM_SIZE:
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self.ram.load(address, data)
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def read_byte(self, cycle, address):
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if address < self.cfg.RAM_SIZE:
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return self.ram.read_byte(address)
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elif address < self.cfg.ROM_START:
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return self.bus_read(cycle, address)
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else:
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return self.rom.read_byte(address)
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def read_word(self, cycle, address):
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return self.read_byte(cycle, address) + (self.read_byte(cycle + 1, address + 1) << 8)
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def bus_read(self, cycle, address):
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if not self.use_bus:
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return 0
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op = struct.pack("<IBHB", cycle, 0, address, 0)
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try:
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self.bus.send(op)
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b = self.bus.recv(1)
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if len(b) == 0:
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sys.exit(0)
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return ord(b)
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except socket.error:
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sys.exit(0)
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def bus_write(self, cycle, address, value):
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if not self.use_bus:
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return
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op = struct.pack("<IBHB", cycle, 1, address, value)
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try:
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self.bus.send(op)
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except IOError:
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sys.exit(0)
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@ -0,0 +1,22 @@
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import inspect
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class BaseConfig(object):
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LOCAL_HOST_IP = "127.0.0.1"
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def print_debug_info(self):
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print "Config: '%s'" % self.__class__.__name__
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for name, value in inspect.getmembers(self): # , inspect.isdatadescriptor):
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if name.startswith("_"):
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continue
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# print name, type(value)
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if not isinstance(value, (int, basestring, list, tuple, dict)):
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continue
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if isinstance(value, (int,)):
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print "%20s = %-4s (in hex: %7s)" % (
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name, value, repr(hex(value))
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)
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else:
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print "%20s = %s" % (name, value)
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