further work in progress to get step motors working correctly on disk drive
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parent
e6e0b2bfc6
commit
84b77572b6
64
applepy.py
64
applepy.py
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@ -328,11 +328,17 @@ class IO:
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slot, switch = divmod(address - 0xC080, 0x10)
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if self.slots[slot] is not None:
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return self.slots[slot].switch(cycle, switch)
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else:
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print "%04X" % address
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return 0x00
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elif 0xC100 <= address <= 0xC7FF:
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hi, lo = divmod(address, 0x100)
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slot = hi - 0xC0
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if self.slots[slot] is not None:
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return self.slots[slot].read_byte(lo)
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else:
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print "%04X" % address
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return 0x00
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elif address == 0xC000:
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return self.kbd
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elif address == 0xC010:
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@ -402,35 +408,55 @@ class DiskController:
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0x4c, 0x01, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
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]
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def __init__(self):
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self.phases = [0, 0, 0, 0]
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self.track_index = 11
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def switch(self, cycle, address):
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assert 0x00 <= address <= 0x0F
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if address == 0x00:
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print "phase 0 off"
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elif address == 0x01:
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print "phase 0 on"
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elif address == 0x02:
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print "phase 1 off"
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elif address == 0x03:
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print "phase 1 off"
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elif address == 0x04:
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print "phase 2 off"
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elif address == 0x05:
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print "phase 2 on"
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elif address == 0x06:
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print "phase 3 off"
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elif address == 0x07:
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print "phase 3 on"
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if 0x00 <= address <= 0x07:
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phase, on = divmod(address, 2)
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self.phases[phase] = on
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current_phase = self.track_index & 0x7
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if self.phases == [1, 0, 0, 0] or self.phases == [1, 1, 0, 1]:
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next_phase = 0
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elif self.phases == [1, 1, 0, 0]:
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next_phase = 1
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elif self.phases == [0, 1, 0, 0] or self.phases == [1, 1, 1, 0]:
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next_phase = 2
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elif self.phases == [0, 1, 1, 0]:
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next_phase = 3
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elif self.phases == [0, 0, 1, 0] or self.phases == [0, 1, 1, 1]:
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next_phase = 4
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elif self.phases == [0, 0, 1, 1]:
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next_phase = 5
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elif self.phases == [0, 0, 0, 1] or self.phases == [1, 0, 1, 1]:
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next_phase = 6
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elif self.phases == [1, 0, 0, 1]:
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next_phase = 7
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else: # [0, 0, 0, 0] [1, 0, 1, 0] [0, 1, 0, 1] [1, 1, 1, 1]
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next_phase = current_phase
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phase_difference = ((next_phase - current_phase + 4) & 0x7) - 4
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self.track_index += phase_difference
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if self.track_index < 0:
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self.track_index = 0
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if self.track_index > 69:
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self.track_index = 69
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print "TRACK", self.track_index, phase_difference
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raw_input()
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elif address == 0x09:
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print "motor on"
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elif address == 0x0A:
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print "select drive 1"
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elif address == 0x0C:
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print "read data"
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pass # print "read data"
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elif address == 0x0E:
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print "set read"
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else:
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print "%d %04X" % (cycle, 0xC080 + address)
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raw_input("pause")
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pass # print "%d %04X" % (cycle, 0xC080 + address)
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return 0x00
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def read_byte(self, address):
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