initial slot support and disk controller implementation (although doesn't do anything but debug output yet)

This commit is contained in:
James Tauber 2011-08-17 09:17:06 -04:00
parent a0ef706a55
commit e6e0b2bfc6
1 changed files with 91 additions and 2 deletions

View File

@ -316,10 +316,24 @@ class IO:
self.display = display
self.speaker = speaker
self.cassette = cassette
self.slots = [None] * 8
def add_card(self, slot, card):
assert 0 < slot < 8
self.slots[slot] = card
def read_byte(self, cycle, address):
assert 0xC000 <= address <= 0xCFFF
if address == 0xC000:
if 0xC080 <= address <= 0xC0FF:
slot, switch = divmod(address - 0xC080, 0x10)
if self.slots[slot] is not None:
return self.slots[slot].switch(cycle, switch)
elif 0xC100 <= address <= 0xC7FF:
hi, lo = divmod(address, 0x100)
slot = hi - 0xC0
if self.slots[slot] is not None:
return self.slots[slot].read_byte(lo)
elif address == 0xC000:
return self.kbd
elif address == 0xC010:
self.kbd = self.kbd & 0x7F
@ -346,16 +360,91 @@ class IO:
if self.cassette:
return self.cassette.read_byte(cycle)
else:
print "%04X" % address
pass # print "%04X" % address
return 0x00
class DiskController:
# 16-sector controller
ROM = [
0xa2, 0x20, 0xa0, 0x00, 0xa2, 0x03, 0x86, 0x3c,
0x8a, 0x0a, 0x24, 0x3c, 0xf0, 0x10, 0x05, 0x3c,
0x49, 0xff, 0x29, 0x7e, 0xb0, 0x08, 0x4a, 0xd0,
0xfb, 0x98, 0x9d, 0x56, 0x03, 0xc8, 0xe8, 0x10,
0xe5, 0x20, 0x58, 0xff, 0xba, 0xbd, 0x00, 0x01,
0x0a, 0x0a, 0x0a, 0x0a, 0x85, 0x2b, 0xaa, 0xbd,
0x8e, 0xc0, 0xbd, 0x8c, 0xc0, 0xbd, 0x8a, 0xc0,
0xbd, 0x89, 0xc0, 0xa0, 0x50, 0xbd, 0x80, 0xc0,
0x98, 0x29, 0x03, 0x0a, 0x05, 0x2b, 0xaa, 0xbd,
0x81, 0xc0, 0xa9, 0x56, 0x20, 0xa8, 0xfc, 0x88,
0x10, 0xeb, 0x85, 0x26, 0x85, 0x3d, 0x85, 0x41,
0xa9, 0x08, 0x85, 0x27, 0x18, 0x08, 0xbd, 0x8c,
0xc0, 0x10, 0xfb, 0x49, 0xd5, 0xd0, 0xf7, 0xbd,
0x8c, 0xc0, 0x10, 0xfb, 0xc9, 0xaa, 0xd0, 0xf3,
0xea, 0xbd, 0x8c, 0xc0, 0x10, 0xfb, 0xc9, 0x96,
0xf0, 0x09, 0x28, 0x90, 0xdf, 0x49, 0xad, 0xf0,
0x25, 0xd0, 0xd9, 0xa0, 0x03, 0x85, 0x40, 0xbd,
0x8c, 0xc0, 0x10, 0xfb, 0x2a, 0x85, 0x3c, 0xbd,
0x8c, 0xc0, 0x10, 0xfb, 0x25, 0x3c, 0x88, 0xd0,
0xec, 0x28, 0xc5, 0x3d, 0xd0, 0xbe, 0xa5, 0x40,
0xc5, 0x41, 0xd0, 0xb8, 0xb0, 0xb7, 0xa0, 0x56,
0x84, 0x3c, 0xbc, 0x8c, 0xc0, 0x10, 0xfb, 0x59,
0xd6, 0x02, 0xa4, 0x3c, 0x88, 0x99, 0x00, 0x03,
0xd0, 0xee, 0x84, 0x3c, 0xbc, 0x8c, 0xc0, 0x10,
0xfb, 0x59, 0xd6, 0x02, 0xa4, 0x3c, 0x91, 0x26,
0xc8, 0xd0, 0xef, 0xbc, 0x8c, 0xc0, 0x10, 0xfb,
0x59, 0xd6, 0x02, 0xd0, 0x87, 0xa0, 0x00, 0xa2,
0x56, 0xca, 0x30, 0xfb, 0xb1, 0x26, 0x5e, 0x00,
0x03, 0x2a, 0x5e, 0x00, 0x03, 0x2a, 0x91, 0x26,
0xc8, 0xd0, 0xee, 0xe6, 0x27, 0xe6, 0x3d, 0xa5,
0x3d, 0xcd, 0x00, 0x08, 0xa6, 0x2b, 0x90, 0xdb,
0x4c, 0x01, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
]
def switch(self, cycle, address):
assert 0x00 <= address <= 0x0F
if address == 0x00:
print "phase 0 off"
elif address == 0x01:
print "phase 0 on"
elif address == 0x02:
print "phase 1 off"
elif address == 0x03:
print "phase 1 off"
elif address == 0x04:
print "phase 2 off"
elif address == 0x05:
print "phase 2 on"
elif address == 0x06:
print "phase 3 off"
elif address == 0x07:
print "phase 3 on"
elif address == 0x09:
print "motor on"
elif address == 0x0A:
print "select drive 1"
elif address == 0x0C:
print "read data"
elif address == 0x0E:
print "set read"
else:
print "%d %04X" % (cycle, 0xC080 + address)
raw_input("pause")
return 0x00
def read_byte(self, address):
assert 0x00 <= address <= 0xFF
return DiskController.ROM[address]
class Apple2:
def __init__(self, options, display, speaker, cassette):
self.display = display
self.speaker = speaker
self.io = IO(display, speaker, cassette)
self.io.add_card(6, DiskController())
args = [
sys.executable,