139 lines
3.4 KiB
Plaintext
139 lines
3.4 KiB
Plaintext
There are two ways we could represent cycle information:
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1. just have an array of cycles for each opcode + the adjustment for
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page boundary crossing (which seems opcode-specific, oddly)
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2. add cycles in individual methods like those accessing memory and the
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operations themselves, to model *why* something takes the cycles it does.
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I prefer 2 on the grounds of it being more instructive but it assumes that
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the way we do things is closely aligned to the way the 6502 is doing them
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internally. Even if we end up having to do 1, I'd love to understand and
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document some of the "why".
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What follows is an attempt to "find the patterns" in the cycle times (as
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given on http://www.6502.org/tutorials/6502opcodes.html )
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NOTE: there appears to be an error in AND and ORA zero page timings on that
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webpage given above. I've now corrected this below.
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There are 10 classes of instructions when it comes to cycle times:
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Class I
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(followed by ADC, AND, BIT, CMP, CPX, CPY, EOR, LDA, LDX, LDY, ORA, SBC, STA,
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STX, STY)
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immediate 2
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zero page 3
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zero page, x 4
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zero page, y 4
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absolute 4
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absolute, x 4 (+1 if page crossed or writing)
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absolute, y 4 (+1 if page crossed or writing)
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indirect, x 6
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indirect, y 5 (+1 if page crossed or writing)
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Note 1: the zero page indexed and x-index indirect don't have the page cross
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addition because they wrap.
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Note 2: writes to indexed non-zero-page memory (e.g. STA) have the +1 even
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if not page crossing.
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Class II
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(followed by ASL, DEC, INC, LSR, ROL, ROR)
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implied 2
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zero page 5
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zero page, x 6
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absolute 6
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absolute, x 7
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Note 3: these take 2 cycles longer than Class I because they involve a
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read-modify-write. Because the absolute, x is a write to an indexed
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non-zero-page memory location, there is an additional +1 even if not page
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crossing (see Note 2)
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Class IIIa
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(followed by CLC, CLD, CLI, CLV, DEX, DEY, INX, INY, NOP, SEC, SED, SEI, TAX,
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TAY, TSX, TXA, TXS, TYA)
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implied 2
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Class IIIb
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(followed by PHA, PHP)
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implied 3
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Class IIIc
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(followed by PLA, PLP)
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implied 4
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Class IIId
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(followed by RTI, RTS)
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implied 6
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Class IIIe
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(followed by BRK)
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implied 7
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Class IV
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(followed by BCC, BCS, BEQ, BMI, BNE, BPL, BVC, BVS)
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branch not taken 2
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branch taken 3 (+1 if page crossed)
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Class V
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(followed by JMP)
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absolute 3
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indirect 5
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Class VI
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(followed by JSR)
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absolute 6
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This seems a possible implementation (not yet considering page boundaries):
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1. all instructions start with 2
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2. absolute (including absolute indexed) adds 2
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3. absolute indexed adds an additional 1 *if* instruction is of RMW type
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4. zero page (including zero page indexed) adds 1
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5. zero page indexed adds an addition 1
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6. indirect (JMP) adds 4
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7. indirect x adds 4
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8. indirect y adds 3 plus an additional 1 *if* instruction is of RMW type
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9. ASL, LSR, ROL, ROR add 2 cycles if not implied
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10. JMP subtracts 1 cycle
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11. JSR adds 2
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12. RTS adds 4
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13. branches add 1 if taken
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14. DEC and INC add 2 cycles
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15. PHA and PHP add 1 cycle
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16. PLA and PLP add 2 cycles
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17. BRK adds 5 cycles
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18. RTI adds 4 cycles
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RMW instructions are the absolute,x of ASL, DEC, INC, LSR ROL, ROR and STA
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as well as indirect,y and absolute,y of STA
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It may be possible to simplify even further given the particular functions
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some of these share in command (where the cycle change could be placed
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instead)
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