2017-05-11 23:23:08 +00:00
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"""Partial simulation of Apple II"""
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2017-05-19 21:41:56 +00:00
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import sqlite3
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import memory
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2017-05-11 23:23:08 +00:00
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from py65.devices import mpu65c02
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2017-05-19 21:41:56 +00:00
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DB_PATH = '/tank/apple2/data/apple2.db'
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MODE_READ = 0x1
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MODE_WRITE = 0x2
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MODE_RW = MODE_READ | MODE_WRITE
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class Event(object):
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def __init__(self, event_type, details):
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self.event_type = event_type
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self.details = details
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def __str__(self):
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return "Event(%s): %s" % (self.event_type, self.details)
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def _Event(region, message):
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def _Event(cpu):
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print "%s event: %s" % (region, message)
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return _Event
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class TrapException(Exception):
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def __init__(self, address, msg):
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self.address = address
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self.msg = msg
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def __str__(self):
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return "$%04X: %s" % (self.address, self.msg)
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2017-05-11 23:23:08 +00:00
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class AppleII(object):
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def __init__(self):
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2017-05-19 21:41:56 +00:00
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memory_map = [
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memory.MemoryRegion("Zero page", 0x0000, 0x00ff),
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memory.MemoryRegion("Stack", 0x0100, 0x01ff),
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memory.MemoryRegion(
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"Text page 1", 0x0400, 0x7ff,
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write_interceptor=self.TextPageWriteInterceptor),
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memory.MemoryRegion(
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"IO page", 0xc000, 0xc0ff, read_interceptor=self.IOInterceptor,
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write_interceptor=self.IOInterceptor),
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memory.MemoryRegion("Slot 1 ROM", 0xc100, 0xc1ff, writable=False),
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memory.MemoryRegion("Slot 2 ROM", 0xc200, 0xc2ff, writable=False),
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memory.MemoryRegion("Slot 3 ROM", 0xc300, 0xc3ff, writable=False),
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memory.MemoryRegion("Slot 4 ROM", 0xc400, 0xc4ff, writable=False),
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memory.MemoryRegion("Slot 5 ROM", 0xc500, 0xc5ff, writable=False),
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memory.MemoryRegion("Slot 6 ROM", 0xc600, 0xc6ff,
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entrypoints={
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0xc65c: self._ReadDiskSector
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},
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writable=False
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),
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memory.MemoryRegion("Slot 7 ROM", 0xc700, 0xc7ff, writable=False),
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memory.MemoryRegion(
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"ROM", 0xd000, 0xffff,
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entrypoints={
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0xfca8: self._Wait,
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0xfe89: _Event("ROM", "Select the keyboard (IN#0)")
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},
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writable=False
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)
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]
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self.memory_manager = memory.MemoryManager(memory_map)
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self.memory = self.memory_manager.memory
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2017-05-11 23:23:08 +00:00
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self.cpu = mpu65c02.MPU(memory=self.memory)
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# Set up interceptors for accessing various interesting parts of the memory map
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2017-05-19 21:41:56 +00:00
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self.io_map = {
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0xc007: (MODE_WRITE, "Turn CXROM switch on"),
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0xc015: (MODE_READ, "Status of Peripheral/CXROM Access"),
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0xc051: (MODE_READ, "Display text"),
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0xc054: (MODE_READ, "Text page 1"),
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0xc056: (MODE_READ, "Enter lores mode"),
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# Slot 6 Disk II
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0xc0e0: (MODE_READ, "phase 0 off"),
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0xc0e1: (MODE_READ, "phase 0 on"),
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0xc0e2: (MODE_READ, "phase 1 off"),
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0xc0e3: (MODE_READ, "phase 1 on"),
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0xc0e4: (MODE_READ, "phase 2 off"),
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0xc0e5: (MODE_READ, "phase 2 on"),
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0xc0e6: (MODE_READ, "phase 3 off"),
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0xc0e7: (MODE_READ, "phase 3 on"),
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0xc0e8: (MODE_READ, "Drives off"),
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0xc0e9: (MODE_READ, "Selected drive on"),
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0xc0ea: (MODE_READ, "Select drive 1"),
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0xc0eb: (MODE_READ, "Select drive 2"),
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0xc0ec: (MODE_READ, "Shift while writing/read data"),
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0xc0ed: (MODE_READ, "Shift while writing/read data"),
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0xc0ee: (MODE_READ, "Enabling disk read mode."),
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0xc0ef: (MODE_READ, "Enabling disk write mode."),
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}
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# Need the ability to intercept execution, e.g. for the C65C sector read routine.
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def IOInterceptor(self, address, value=None):
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access_mode = MODE_READ if (value == None) else MODE_WRITE
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try:
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(mode, result) = self.io_map[address]
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if access_mode & mode:
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print "==== IO EVENT: %s" % result
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else:
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print "**** IO EVENT with unexpected mode: %s" % result
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except KeyError:
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if value:
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print TrapException(address, 'Wrote %02X ("%s")' % (value, chr(value)))
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else:
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print TrapException(address, 'Read')
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2017-05-11 23:23:08 +00:00
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2017-05-19 21:41:56 +00:00
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def _ReadDiskSector(self, cpu):
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print "Read disk sector from Track $%02X Sector $%02X" % (self.memory[0x41], self.memory[0x3d])
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cpu.pc = 0x801
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def _Wait(self, cpu):
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print "Waiting"
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2017-05-11 23:23:08 +00:00
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# TODO: convert addresses to screen coordinates
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2017-05-19 21:41:56 +00:00
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# See e.g. https://retrocomputing.stackexchange.com/questions/2534/what-are-the-screen-holes-in-apple-ii-graphics
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2017-05-11 23:23:08 +00:00
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def TextPageWriteInterceptor(self, address, value):
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print 'Wrote "%s" to text page address $%04X' % (chr(value & 0x7f), address)
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2017-05-19 21:41:56 +00:00
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def Run(self, pc, trace=False):
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2017-05-11 23:23:08 +00:00
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self.cpu.pc = pc
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2017-05-19 21:41:56 +00:00
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old_pc = self.cpu.pc
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2017-05-11 23:23:08 +00:00
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while True:
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2017-05-19 21:41:56 +00:00
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self.memory_manager.MaybeInterceptExecution(self.cpu, old_pc)
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old_pc = self.cpu.pc
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self.cpu.step(trace=trace)
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if self.cpu.pc == old_pc:
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2017-05-11 23:23:08 +00:00
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break
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def main():
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2017-05-19 21:41:56 +00:00
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conn = sqlite3.connect(DB_PATH)
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cursor = conn.cursor()
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2017-05-11 23:23:08 +00:00
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2017-05-19 21:41:56 +00:00
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# Load the most popular boot1
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# q = cursor.execute(
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# """
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# select boot1_sha1, boot1.data, count(*) from disks
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# join
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# (select sha1, data from boot1) as boot1
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# on disks.boot1_sha1 = boot1.sha1 group by 1 order by 3 desc limit 1
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# """
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# )
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# Dos 3.3
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q = cursor.execute(
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"""
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select data from boot1 where sha1 = '7ab36247fdf62e87f98d2964dd74d6572d17fff0'
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"""
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)
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for r in q:
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(boot1,) = r
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#
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# # boot1 image that prints stuff to the text page without using ROM entrypoints
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# q = cursor.execute(
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# """
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# select data from boot1 where sha1 = '62bda735bcb4a27ffbd833ebb4ff2503b983ea97'
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# """
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# )
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for r in q:
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(boot1,) = r
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2017-05-11 23:23:08 +00:00
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apple2 = AppleII()
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2017-05-19 21:41:56 +00:00
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# Read in Apple IIE ROM image
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rom = bytearray(open("APPLE2E.ROM", "r").read())
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# XXX these should write-trap
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# Slot 6 ROM
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apple2.memory[0xc600:0xc6ff] = rom[0x0600:0x6ff]
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# Main ROM
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apple2.memory[0xd000:0xffff] = rom[0x5000:0x7fff]
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# TODO: why does this not use the 6502 reset vector?
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apple2.cpu.reset()
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apple2.memory[0x800:0x800 + len(boot1)] = bytearray(boot1)
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# Disk II firmware stores next page load address here
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apple2.memory[0x26] = 0x00
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apple2.memory[0x27] = 0x09
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# "3" is used for controller ID
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apple2.memory[0x3c] = 0x03
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# Sector to read
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apple2.memory[0x3d] = 0x00
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# Track to read
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apple2.memory[0x41] = 0x00
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# Booting from slot 6
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apple2.memory[0x2b] = 0x60
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#apple2.Run(0xfa62) # Target of 6502 reset vector
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apple2.Run(0x801, trace=True)
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2017-05-11 23:23:08 +00:00
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if __name__ == '__main__':
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2017-05-19 21:41:56 +00:00
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main()
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