mirror of
https://github.com/bradgrantham/apple2e.git
synced 2024-11-18 05:11:48 +00:00
604bf07b4f
Floppy disks partially work:
apple2e -noaudio -fast -diskII disk2romfile {floppy1name,"none"} {floppy2name,"none"} apple2e.rom
Import nybblizer from Shamus but only DOS
Support floppy hardware
track motor stepper
enable
read
Add -noaudio (otherwise execution is throttled by waits once audio buffer is filled)
Only read ROM at D000 and E000 if C08X_read_RAM isn't turned on
RAMRD, RAMWRT, and ALTZP are implemented, note them as such in constructor
Correctly decode C08X soft switches
Implement a bunch more instructions
INC abs
LDY abs, X
SBC abs, Y
ADC abs
ASL abs
LSR abs, X
ORA abs
ORA abs, X
AND abs, Y
STA (ind, X)
LDX abs
CPX abs
EOR (ind, X)
EOR abs
EOR abs, X
STX abs
Throttle to actual number of clocks per instruction
Temporarily enable "Fake6502" instead of my CPU because there's an obvious difference
Better blink speed in interface.cpp
98 lines
5.7 KiB
Plaintext
98 lines
5.7 KiB
Plaintext
soft switch with W 2 addresses, read high bit
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C002 49154 RDMAINRAM ECG W If 80STORE Off: Read Main Mem $0200-$BFFF
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C003 49155 RDCARDRAM ECG W If 80STORE Off: Read Aux Mem $0200-$BFFF
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C013 49171 RDRAMRD ECG R7 Status of Main/Aux RAM Reading
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C004 49156 WRMAINRAM ECG W If 80STORE Off: Write Main Mem $0200-$BFFF
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C005 49157 WRCARDRAM ECG W If 80STORE Off: Write Aux Mem $0200-$BFFF
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C014 49172 RDRAMWRT ECG R7 Status of Main/Aux RAM Writing
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C006 49158 SETSLOTCXROM E G W Peripheral ROM ($C100-$CFFF)
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C007 49159 SETINTCXROM E G W Internal ROM ($C100-$CFFF)
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C015 49173 RDCXROM E G R7 Status of Periph/ROM Access
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C008 49160 SETSTDZP ECG W Main Stack and Zero Page
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C009 49161 SETALTZP ECG W Aux Stack and Zero Page
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C016 49174 RDALTZP ECG R7 Status of Main/Aux Stack and Zero Page
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C00A 49162 SETINTC3ROM E G W ROM in Slot 3
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C00B 49163 SETSLOTC3ROM E G W ROM in Aux Slot
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C017 49175 RDC3ROM E G R7 Status of Slot 3/Aux Slot ROM
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C000 80STOREOFF ECG W Use $C002-$C005 for Aux Memory
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C001 49153 80STOREON ECG W Use PAGE2 for Aux Memory
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C018 49176 RD80STORE ECG R7 Status of $C002-$C005/PAGE2 for Aux Mem
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C00E 49166 CLRALTCHAR ECG W Primary Character Set
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C00F 49167 SETALTCHAR ECG W Alternate Character Set
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C01E 49182 RDALTCHAR ECG R7 Status of Primary/Alternate Character Set
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C00C 49164 CLR80VID ECG W 40 Columns
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C00D 49165 SET80VID ECG W 80 Columns
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C01F 49183 RD80VID ECG R7 Status of 40/80 Columns
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???
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C011 49169 RDLCBNK2 ECG R7 Status of Selected $Dx Bank
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C012 49170 RDLCRAM ECG R7 Status of $Dx ROM / $Dx RAM
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soft switch with R/W 2 addresses, read high bit
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C050 49232 TXTCLR OECG WR Display Graphics
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C051 49233 TXTSET OECG WR Display Text
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C01A 49178 RDTEXT ECG R7 Status of Text/Graphics
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C052 49234 MIXCLR OECG WR Display Full Screen
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C053 49235 MIXSET OECG WR Display Split Screen
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C01B 49179 RDMIXED ECG R7 Status of Full Screen/Mixed Graphics
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C054 49236 TXTPAGE1 OECG WR Display Page 1
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C055 49237 TXTPAGE2 OECG WR If 80STORE Off: Display Page 2
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ECG WR If 80STORE On: Read/Write Aux Display Mem
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C01C 49180 RDPAGE2 ECG R7 Status of Page 1/Page 2
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C056 49238 LORES OECG WR Display LoRes Graphics
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C057 49239 HIRES OECG WR Display HiRes Graphics
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C01D 49181 RDHIRES ECG R7 Status of LoRes/HiRes
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C000 49152 KBD OECG R Last Key Pressed + 128
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C010 49168 KBDSTRB OECG WR Keyboard Strobe
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C019 49177 RDVBL E G R7 Vertical Blanking (E:1=drawing G:0=drawing)
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C020 49184 TAPEOUT OE R Toggle Cassette Tape Output
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C028 49192 ROMBANK ???? ROM bank select toggle
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C02C 49196 CHARROM ???? Addr for test mode read of character ROM
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C02E 49198 VERTCNT ???? Addr for read of video cntr bits V5-VB
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C02F 49199 HORIZCNT ???? Addr for read of video cntr bits VA-H0
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C030 48200 SPKR OECG R Toggle Speaker
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C040 49216 STROBE OE R Game I/O Strobe Output
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C058 49240 CLRAN0 OE G WR If IOUDIS off: Annunciator 0 Off
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C059 49241 SETAN0 OE G WR If IOUDIS off: Annunciator 0 On
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C05A 49242 CLRAN1 OE G WR If IOUDIS off: Annunciator 1 Off
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C05B 49243 SETAN1 OE G WR If IOUDIS off: Annunciator 1 On
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C05C 49244 CLRAN2 OE G WR If IOUDIS off: Annunciator 2 Off
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C05D 49245 SETAN2 OE G WR If IOUDIS off: Annunciator 2 On
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C05E 49246 CLRAN3 OE G WR If IOUDIS off: Annunciator 3 Off
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DHIRESON ECG WR In 80-Column Mode: Double Width Graphics
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C05F 49247 SETAN3 OE G WR If IOUDIS off: Annunciator 3 On
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DHIRESOFF ECG WR In 80-Column Mode: Single Width Graphics
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C060 49248 TAPEIN OE R7 Read Cassette Input
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C061 49249 RDBTN0 ECG R7 Switch Input 0 / Open Apple
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C062 49250 BUTN1 E G R7 Switch Input 1 / Solid Apple
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C063 49251 RD63 E G R7 Switch Input 2 / Shift Key
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C064 49252 PADDL0 OECG R7 Analog Input 0
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C065 49253 PADDL1 OECG R7 Analog Input 1
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C066 49254 PADDL2 OE G R7 Analog Input 2
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C067 49255 PADDL3 OE G R7 Analog Input 3
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C070 49264 PTRIG E R Analog Input Reset
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C073 49267 BANKSEL ECG W Memory Bank Select for > 128K
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C07E 49278 IOUDISON EC W Disable IOU
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RDIOUDIS EC R7 Status of IOU Disabling
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C07F 49279 IOUDISOFF EC W Enable IOU
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RDDHIRES EC R7 Status of Double HiRes
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C080 49280 OECG R Read RAM bank 2; no write
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C081 49281 ROMIN OECG RR Read ROM; write RAM bank 2
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C082 49282 OECG R Read ROM; no write
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C083 49283 LCBANK2 OECG RR Read/write RAM bank 2
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C084 49284 OECG R Read RAM bank 2; no write
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C085 49285 ROMIN OECG RR Read ROM; write RAM bank 2
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C086 49286 OECG R Read ROM; no write
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C087 49287 LCBANK2 OECG RR Read/write RAM bank 2
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C088 49288 OECG R Read RAM bank 1; no write
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C089 49289 OECG RR Read ROM; write RAM bank 1
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C08A 49290 OECG R Read ROM; no write
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C08B 49291 OECG RR Read/write RAM bank 1
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C08C 49292 OECG R Read RAM bank 1; no write
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C08D 49293 OECG RR Read ROM; write RAM bank 1
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C08E 49294 OECG R Read ROM; no write
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C08F 49295 OECG RR Read/write RAM bank 1
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