mirror of
https://github.com/bradgrantham/apple2e.git
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54 lines
3.1 KiB
Plaintext
54 lines
3.1 KiB
Plaintext
per-scanline modes
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Actual Apple II TEXT/GR and HGR video address patterns are in Understanding the Apple II
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Not for DHGR or 80-col but they're probably just same address twice alternating banks
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tracking clock and reporting video memory contents
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clock
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one tick of ~1MHz clock maps to one tick of address counter
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so is 7 HGR bits or one GR/TEXT horizontal cell
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"most 6502 cycles are 978 nS long [14 14mhz clocks], but every 65th cycle is 1117 nS long [16 14mhz clocks]."
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source clock is 14.31818MHz
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unsigned long would overflow after 20 minutes
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Could modulo byteclock by 14318180 at iterate() and not overflow
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as long as it doesn't take longer than 20 minutes between calls to APPLE2Einterface::iterate than 20 minutes...)
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Could have clk be in 14MHz ticks.
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unsigned long long will last 40853 years (could be slow on embedded systems)
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Keep track of phase at clk delta time, and add 14 usually but 16 every 65th
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Then wall clock is just always ticks / 14318180.0
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phase_hpe initially 0
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add_cpu_cycles(elapsed_cpu) {
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clock_cpu += elapsed_cpu
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clock_14mhz = elapsed_cpu * 14 + (elapsed_cpu + phase_hpe) / 65 * 16
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phase_hpe = (phase_hpe + elapsed_cpu) % 65
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}
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clock_14mhz is 14mhz ticks
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clock_cpu is CPU clocks, averaging 1.023MHz
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phase_hpe is clock_cpu within horizontal line
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Current CPU clk (in 1MHz CPU cycles) is used for
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which audio sample (at libAO sample rate) in the audio waveform we should fill
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OK - should work with higher fixed rate
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mark after how many cycles the open apple key should be raised
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OK - should work with higher fixed rate
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mark paddle timer
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OK - should work with higher fixed rate
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incrementing CPU instruction cycles
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OK - call add_cpu_cycles()
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address generator
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every line is 65 bytes, there are 262 lines, so there are 17030 bytes per field
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honor softswitches
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convert clock_cpu to address
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blanking and offscreen addressing during HIRES MIXED
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160 through 191 and 224 through 261
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TEXT addressing at 160, HPE' + 1 through at 192, HPE'
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argh
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read empty memory address on bus no longer fails but instead
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generate address, get byte from RAM and return it
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recording softswitch mode changes
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store vector of switch or mode change and byteclock
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instead of setting before APPLE2Einterface::iterate, pass into iterate
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honoring softswitch change in APPLE2Einterface
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initialize scanline mode array to text
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receive vector of tuple of byteclock and modes
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fill scanline mode array from passed in vector
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draw framebuffer by scanline
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