mirror of
https://github.com/st3fan/ewm.git
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192 lines
6.1 KiB
C
192 lines
6.1 KiB
C
// The MIT License (MIT)
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//
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// Copyright (c) 2015 Stefan Arentz - http://github.com/st3fan/ewm
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all
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// copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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#include <stdbool.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include "cpu.h"
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#include "alc.h"
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uint8_t alc_iom_read(struct cpu_t *cpu, struct mem_t *mem, uint16_t addr) {
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struct ewm_alc_t *alc = (struct ewm_alc_t*) mem->obj;
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// Always enable the right banks
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if (addr & 0b00001000) {
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alc->ram1->enabled = true;
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alc->ram2->enabled = false;
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alc->ram3->enabled = true;
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} else {
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alc->ram1->enabled = false;
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alc->ram2->enabled = true;
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alc->ram3->enabled = true;
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}
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switch (addr) {
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// WRTCOUNT = 0, WRITE DISABLE, READ ENABLE
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case 0xc080:
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case 0xc084:
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alc->wrtcount = 0;
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alc->ram1->flags = MEM_FLAGS_READ;
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alc->ram2->flags = MEM_FLAGS_READ;
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alc->ram3->flags = MEM_FLAGS_READ;
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break;
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// WRTCOUNT++, READ DISABLE, WRITE ENABLE IF WRTCOUNT >= 2
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case 0xc081:
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case 0xc085:
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alc->wrtcount = alc->wrtcount + 1;
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alc->ram1->flags &= ~MEM_FLAGS_READ;
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alc->ram2->flags &= ~MEM_FLAGS_READ;
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alc->ram3->flags &= ~MEM_FLAGS_READ;
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if (alc->wrtcount >= 2) {
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alc->ram1->flags |= MEM_FLAGS_WRITE;
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alc->ram2->flags |= MEM_FLAGS_WRITE;
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alc->ram3->flags |= MEM_FLAGS_WRITE;
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}
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break;
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// WRTCOUNT = 0, WRITE DISABLE, READ DISABLE
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case 0xc082:
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case 0xc086:
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alc->wrtcount = 0;
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alc->ram1->flags &= ~MEM_FLAGS_WRITE;
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alc->ram2->flags &= ~MEM_FLAGS_WRITE;
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alc->ram3->flags &= ~MEM_FLAGS_WRITE;
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alc->ram1->flags &= MEM_FLAGS_WRITE;
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alc->ram2->flags &= MEM_FLAGS_WRITE;
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alc->ram3->flags &= MEM_FLAGS_WRITE;
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break;
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// WRTCOUNT++, READ ENABLE, WRITE ENABLE IF WRTCOUNT >= 2
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case 0xc083:
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case 0xc08b:
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alc->wrtcount = alc->wrtcount + 1;
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alc->ram1->flags |= MEM_FLAGS_READ;
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alc->ram2->flags |= MEM_FLAGS_READ;
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alc->ram3->flags |= MEM_FLAGS_READ;
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if (alc->wrtcount >= 2) {
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alc->ram1->flags |= MEM_FLAGS_WRITE;
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alc->ram2->flags |= MEM_FLAGS_WRITE;
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alc->ram3->flags |= MEM_FLAGS_WRITE;
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}
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break;
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default:
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fprintf(stderr, "[ALC] Unexpected read at $%.4X\n", addr);
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break;
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}
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return 0;
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}
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static void alc_iom_write(struct cpu_t *cpu, struct mem_t *mem, uint16_t addr, uint8_t b) {
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struct ewm_alc_t *alc = (struct ewm_alc_t*) mem->obj;
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// Always enable the right banks
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if (addr & 0b00001000) {
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alc->ram1->enabled = true;
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alc->ram2->enabled = false;
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alc->ram3->enabled = true;
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} else {
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alc->ram1->enabled = false;
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alc->ram2->enabled = true;
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alc->ram3->enabled = true;
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}
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switch (addr) {
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// WRTCOUNT = 0, WRITE DISABLE, READ ENABLE
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case 0xc080:
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case 0xc084:
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alc->wrtcount = 0;
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alc->ram1->flags = MEM_FLAGS_READ;
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alc->ram2->flags = MEM_FLAGS_READ;
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alc->ram3->flags = MEM_FLAGS_READ;
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break;
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// WRTCOUNT = 0, READ DISABLE
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case 0xc081:
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case 0xc085:
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alc->wrtcount = 0;
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alc->ram1->flags &= ~MEM_FLAGS_READ;
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alc->ram2->flags &= ~MEM_FLAGS_READ;
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alc->ram3->flags &= ~MEM_FLAGS_READ;
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break;
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// WRTCOUNT = 0, WRITE DISABLE, READ DISABLE
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case 0xc082:
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case 0xc086:
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alc->wrtcount = 0;
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alc->ram1->flags &= ~MEM_FLAGS_WRITE;
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alc->ram2->flags &= ~MEM_FLAGS_WRITE;
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alc->ram3->flags &= ~MEM_FLAGS_WRITE;
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alc->ram1->flags &= MEM_FLAGS_WRITE;
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alc->ram2->flags &= MEM_FLAGS_WRITE;
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alc->ram3->flags &= MEM_FLAGS_WRITE;
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break;
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// WRTCOUNT = 0, READ ENABLE
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case 0xc083:
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case 0xc08b:
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alc->wrtcount = 0;
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alc->ram1->flags |= MEM_FLAGS_READ;
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alc->ram2->flags |= MEM_FLAGS_READ;
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alc->ram3->flags |= MEM_FLAGS_READ;
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break;
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default:
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fprintf(stderr, "[ALC] Unexpected write at $%.4X\n", addr);
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break;
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}
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}
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int ewm_alc_init(struct ewm_alc_t *alc, struct cpu_t *cpu) {
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memset(alc, 0x00, sizeof(struct ewm_alc_t));
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// Order is important. First added is last tried when looking up
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// addresses. So we register the ROM first, which means we never
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// have to disable it.
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alc->rom = cpu_add_rom_file(cpu, 0xf800, "roms/341-0020.bin");
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alc->iom = cpu_add_iom(cpu, 0xc080, 0xc08f, alc, alc_iom_read, alc_iom_write);
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alc->ram1 = cpu_add_ram(cpu, 0xd000, 0xd000 + 4096 - 1);
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alc->ram2 = cpu_add_ram(cpu, 0xd000, 0xd000 + 4096 - 1);
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alc->ram3 = cpu_add_ram(cpu, 0xe000, 0xe000 + 8192 - 1);
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alc->ram1->enabled = false;
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alc->ram2->enabled = false;
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alc->ram3->enabled = false;
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return 0;
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}
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struct ewm_alc_t *ewm_alc_create(struct cpu_t *cpu) {
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struct ewm_alc_t *alc = malloc(sizeof(struct ewm_alc_t));
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if (ewm_alc_init(alc, cpu) != 0) {
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free(alc);
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alc = NULL;
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}
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return alc;
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}
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