mirror of https://github.com/LemonBoy/grape.git
65C02 opcodes. The cpu core passes nearly all the tests (fuck you decimal mode). Minor fixes here and there. Lo-res fixes and stuff.
This commit is contained in:
LemonBoy
parent
8e45768c29
commit
d37d6f0bcf
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@ -6,5 +6,14 @@ void cpu_reset ();
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void cpu_nmi ();
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extern u32 cpu_regs[6];
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enum {
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RF = 0,
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RY,
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RX,
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RA,
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RSP,
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RPC,
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};
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#endif
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394
source/cpu.s
394
source/cpu.s
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@ -1,6 +1,10 @@
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.arm
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.section .itcm,"ax",%progbits
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#define UNDOC_OPS
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//#define PRINT_TRACE
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//#define CHECK_IDLE_JUMP
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.global cpu_run
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.global cpu_reset
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.global cpu_regs
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@ -27,16 +31,6 @@ cycles .req r5
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orr r0, r1, lsl #8
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.endm
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.macro rebase_sp r
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ldr r0, =(mainram+0x100)
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add \r, r0
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.endm
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.macro unbase_sp r
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ldr r0, =(mainram+0x100)
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sub \r, reg_sp, r0
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.endm
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.macro rebase_pc r
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ldr r1, =memmap_r
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mov r2, \r, lsr #12
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@ -48,16 +42,22 @@ cycles .req r5
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.macro unbase_pc r
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ldr r1, =last_page
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ldr r2, [r1]
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sub \r, reg_pc, r2
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ldr r1, [r1]
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sub \r, reg_pc, r1
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.endm
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.macro push b
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strb \b, [reg_sp], #-1
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.macro push r
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ldr r3, =(mainram+0x100)
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strb \r, [r3, reg_sp]
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sub reg_sp, #1
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and reg_sp, #255
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.endm
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.macro pop
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ldrb r0, [reg_sp, #1]!
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.macro pop r
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ldr r1, =(mainram+0x100)
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add reg_sp, #1
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and reg_sp, #255
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ldrb \r, [r1, reg_sp]
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.endm
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.macro adr_zp_z
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@ -77,51 +77,71 @@ cycles .req r5
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.macro adr_abs r
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fetchw
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mov r1, r0, lsr #8
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cmp r1, #0xff
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subeq cycles, #1
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add r0, \r
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cmp r1, r0, lsr #8
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// Page crossing adds a penality cycle
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subne cycles, #1
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.endm
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.macro adr_idx
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fetchw
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ldr r1, =memmap_r
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mov r2, r0, lsr #12
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ldr r1, [r1, r2, lsl #2]
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add r1, r0
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ldrb r0, [r1, #0]
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ldrb r1, [r1, #1]
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and r4, r0, #0xff00
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add r3, r0, #1
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and r3, #255
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orr r4, r3
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ldr r2, =memmap_r
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lsr r1, r0, #12
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ldr r3, [r2, r1, lsl #2]
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ldrb r0, [r3, r0]
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lsr r1, r4, #12
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ldr r3, [r2, r1, lsl #2]
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ldrb r1, [r3, r4]
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orr r0, r1, lsl #8
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.endm
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.macro adr_idx_x
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fetch
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ldr r1, =memmap_r
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add r0, reg_x
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ldr r1, [r1]
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add r1, r0
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ldrb r0, [r1, #0]
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ldrb r1, [r1, #1]
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and r0, #255
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ldr r3, =memmap_r
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ldr r3, [r3]
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add r2, r0, #1
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and r2, #255
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ldrb r0, [r3, r0]
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ldrb r1, [r3, r2]
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orr r0, r1, lsl #8
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.endm
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.macro adr_idx_y
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fetch
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ldr r3, =memmap_r
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ldr r2, [r3]
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add r2, r2, r0
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ldrb r0, [r2, #0]
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ldrb r1, [r2, #1]
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ldr r3, [r3]
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add r2, r0, #1
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and r2, #255
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ldrb r0, [r3, r0]
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ldrb r1, [r3, r2]
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orr r0, r1, lsl #8
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add r1, r0, reg_y
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eor r2, r1, r0
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tst r2, #0x100
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add r0, reg_y
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// Page crossing adds a penality cycle
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cmp r1, r0, lsr #8
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subne cycles, #1
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mov r0, r1
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.endm
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.macro adr_rel
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ldrsb r0, [reg_pc], #1
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// Sign extend
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#ifdef CHECK_IDLE_JUMP
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cmp r0, #-2
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bne 2f
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// unbase_pc reg_pc
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// ldr r0, =idle_loop_msg
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// mov r1, reg_pc
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// bl iprintf
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b _xx
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#endif
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2: // Sign extend
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add r2, reg_pc, r0
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eor r1, r2, reg_pc
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tst r1, #0x100
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@ -133,6 +153,7 @@ cycles .req r5
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#define FLAG_ZERO 0x02<<24
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#define FLAG_INTR 0x04<<24
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#define FLAG_DEC 0x08<<24
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#define FLAG_BRK 0x20<<24
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#define FLAG_OVER 0x40<<24
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#define FLAG_NEG 0x80<<24
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@ -147,6 +168,21 @@ cycles .req r5
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orrvs reg_f, #FLAG_OVER
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orrmi reg_f, #FLAG_NEG
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mov reg_a, reg_a, lsr #24
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// Decimal mode
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tst reg_f, #FLAG_DEC
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beq 1f
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bic reg_f, #FLAG_CARRY
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// Low nibble
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and r2, reg_a, #0x0f
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cmp r2, #0x09
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addhi reg_a, #0x06
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// High nibble
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and r1, reg_a, #0xf0<<24
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cmp r1, #0x90
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addhi reg_a, #0x60
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orrhi reg_f, #FLAG_CARRY
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add cycles, #1
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1: nop
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.endm
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.macro op_sbc r
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@ -159,6 +195,22 @@ cycles .req r5
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orrmi reg_f, #FLAG_NEG
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movs reg_a, reg_a, lsr #24
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orreq reg_f, #FLAG_ZERO
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// Decimal mode
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tst reg_f, #FLAG_DEC
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beq 1f
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sub reg_a, #0x66
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bic reg_f, #FLAG_CARRY
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// Low nibble
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and r2, reg_a, #0x0f
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cmp r2, #0x09
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addhi reg_a, #0x06
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// High nibble
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and r1, reg_a, #0xf0<<24
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cmp r1, #0x90
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addhi reg_a, #0x60
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orrhi reg_f, #FLAG_CARRY
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add cycles, #1
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1: nop
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.endm
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.macro op_and a1
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@ -216,11 +268,10 @@ cycles .req r5
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.endm
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.macro op_lsr a1
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bic reg_f, #(FLAG_CARRY+FLAG_ZERO)
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bic reg_f, #(FLAG_CARRY+FLAG_ZERO+FLAG_NEG)
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movs \a1, \a1, lsr #1
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orrcs reg_f, #FLAG_CARRY
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orreq reg_f, #FLAG_ZERO
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//flag_neg \a1
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.endm
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.macro op_ora a1
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@ -264,9 +315,19 @@ cycles .req r5
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orrne reg_f, #FLAG_NEG
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.endm
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.macro op_txb set, a1
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tst \a1, reg_a
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orreq reg_f, #FLAG_ZERO
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bicne reg_f, #FLAG_ZERO
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.if \set == 1
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orr \a1, reg_a
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.else
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bic \a1, reg_a
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.endif
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.endm
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// NOP
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_ea:
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_7a:
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mov r0, #2
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b instr_end
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// ORA
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@ -451,7 +512,6 @@ _2c:
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op_bit r0
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mov r0, #4
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b instr_end
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.ltorg
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// BMI
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_30:
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tst reg_f, #FLAG_NEG
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@ -481,8 +541,8 @@ _10:
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b instr_end
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// BRK
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_00:
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add reg_pc, #1
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unbase_pc r0
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add r0, #1
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mov r1, r0, lsr #8
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and r2, r0, #0xff
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push r1
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@ -490,7 +550,7 @@ _00:
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mov r0, reg_f, lsr #24
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orr r0, #0x30
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push r0
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orr reg_f, #FLAG_INTR
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orr reg_f, #(FLAG_INTR|FLAG_BRK)
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ldr r0, =memmap_r
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ldr r0, [r0, #0xf<<2]
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@ -505,21 +565,18 @@ _00:
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b instr_end
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// RTI
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_40:
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pop
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bic reg_f, #0xff000000
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orr reg_f, r0, lsl #24
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pop
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mov reg_pc, r0
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pop
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pop r0
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mov reg_f, r0, lsl #24
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pop reg_pc
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pop r0
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orr reg_pc, r0, lsl #8
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rebase_pc reg_pc
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mov r0, #6
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b instr_end
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.ltorg
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// RTS
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_60:
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pop
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mov reg_pc, r0
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pop
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pop reg_pc
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pop r0
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orr reg_pc, r0, lsl #8
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add reg_pc, #1
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rebase_pc reg_pc
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@ -543,7 +600,6 @@ _20:
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rebase_pc reg_pc
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mov r0, #6
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b instr_end
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// STX
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_86:
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adr_zp_z
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@ -584,7 +640,6 @@ _a4:
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lsr reg_y, #24
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mov r0, #3
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b instr_end
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.ltorg
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_b4:
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bic reg_f, #(FLAG_ZERO+FLAG_NEG)
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adr_zp reg_x
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@ -782,13 +837,31 @@ _91:
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// JMP
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_4c:
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adr_abs_z
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mov reg_pc, r0
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#ifdef CHECK_IDLE_JUMP
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cmp reg_pc, r0
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bne 2f
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unbase_pc reg_pc
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ldr r0, =idle_loop_msg
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mov r1, reg_pc
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bl iprintf
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1: b 1b
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#endif
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2: mov reg_pc, r0
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rebase_pc reg_pc
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mov r0, #3
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b instr_end
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_6c:
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adr_idx
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mov reg_pc, r0
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#ifdef CHECK_IDLE_JUMP
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cmp reg_pc, r0
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bne 2f
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unbase_pc reg_pc
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ldr r0, =idle_loop_msg
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mov r1, reg_pc
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bl iprintf
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1: b 1b
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#endif
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2: mov reg_pc, r0
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rebase_pc reg_pc
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mov r0, #5
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b instr_end
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@ -800,7 +873,7 @@ _48:
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// PLA
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_68:
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bic reg_f, #(FLAG_ZERO+FLAG_NEG)
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pop
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pop r0
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movs reg_a, r0, lsl #24
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orreq reg_f, #FLAG_ZERO
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orrmi reg_f, #FLAG_NEG
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@ -1246,16 +1319,16 @@ _98:
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// TXS
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_9a:
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mov reg_sp, reg_x
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rebase_sp reg_sp
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mov r0, #2
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b instr_end
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// TSX
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_ba:
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bic reg_f, #(FLAG_ZERO+FLAG_NEG)
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unbase_sp reg_x
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mov reg_x, reg_sp
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movs reg_x, reg_x, lsl #24
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orreq reg_f, #FLAG_ZERO
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movs r1, reg_x, lsl #24
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orrmi reg_f, #FLAG_NEG
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mov reg_x, reg_x, lsr #24
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mov r0, #2
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b instr_end
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// DEC
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@ -1303,13 +1376,13 @@ _18:
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// PHP
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_08:
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mov r0, reg_f, lsr #24
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orr r0, #0x30 // MAGIC!
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orr r0, #0x30 // BRK flag + reserved bit
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push r0
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mov r0, #3
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b instr_end
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// PLP
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_28:
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pop
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pop r0
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mov reg_f, r0, lsl #24
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mov r0, #4
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b instr_end
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@ -1410,6 +1483,11 @@ _b8:
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bic reg_f, #FLAG_OVER
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mov r0, #2
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b instr_end
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#ifdef UNDOC_OPS
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// NOP
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_7a:
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mov r0, #2
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b instr_end
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// LAX
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_b7:
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bic reg_f, #(FLAG_ZERO+FLAG_NEG)
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@ -1444,6 +1522,137 @@ _07:
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op_ora r1
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mov r0, #5
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b instr_end
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_1a:
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_3c:
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_5a:
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_89:
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_93:
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_c7:
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_da:
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_f7:
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_fa:
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_0c:
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_3a:
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_64:
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_74:
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_80:
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_9c:
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_9e:
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b _xx
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#else
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// BIT
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_89:
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fetch
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tst reg_a, r0
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bicne reg_f, #FLAG_ZERO
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orreq reg_f, #FLAG_ZERO
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mov r0, #2
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b instr_end
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_3c:
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adr_abs reg_x
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bl readb
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op_bit r0
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mov r0, #4
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b instr_end
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// PHX
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_da:
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push reg_x
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mov r0, #3
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b instr_end
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// PHY
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_5a:
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push reg_y
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mov r0, #3
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b instr_end
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// PLX
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_fa:
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bic reg_f, #(FLAG_ZERO+FLAG_NEG)
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pop reg_x
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movs reg_x, reg_x, lsl #24
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orreq reg_f, #FLAG_ZERO
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orrmi reg_f, #FLAG_NEG
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lsr reg_x, #24
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mov r0, #4
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b instr_end
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// PLY
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_7a:
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bic reg_f, #(FLAG_ZERO+FLAG_NEG)
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pop reg_y
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movs reg_y, reg_y, lsl #24
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orreq reg_f, #FLAG_ZERO
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orrmi reg_f, #FLAG_NEG
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lsr reg_y, #24
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mov r0, #4
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b instr_end
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// TSB
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_04:
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adr_zp_z
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ldr r1, =mainram
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ldrb r2, [r1, r0]
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op_txb 1, r2
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strb r2, [r1, r0]
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mov r0, #5
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b instr_end
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_0c:
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adr_abs_z
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mov r4, r0
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bl readb
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op_txb 1, r0
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mov r1, r0
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mov r0, r4
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bl writeb
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mov r0, #6
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b instr_end
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// INC
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_1a:
|
||||
op_inc reg_a
|
||||
mov r0, #2
|
||||
b instr_end
|
||||
// DEC
|
||||
_3a:
|
||||
op_dec reg_a
|
||||
mov r0, #2
|
||||
b instr_end
|
||||
// STZ
|
||||
_64:
|
||||
adr_zp_z
|
||||
ldr r1, =mainram
|
||||
mov r2, #0
|
||||
strb r2, [r1, r0]
|
||||
mov r0, #3
|
||||
b instr_end
|
||||
_74:
|
||||
adr_zp reg_x
|
||||
ldr r1, =mainram
|
||||
mov r2, #0
|
||||
strb r2, [r1, r0]
|
||||
mov r0, #3
|
||||
b instr_end
|
||||
_9c:
|
||||
adr_abs_z
|
||||
mov r1, #0
|
||||
bl writeb
|
||||
mov r0, #4
|
||||
b instr_end
|
||||
_9e:
|
||||
adr_abs reg_x
|
||||
mov r1, #0
|
||||
bl writeb
|
||||
mov r0, #4
|
||||
b instr_end
|
||||
// BRA
|
||||
_80:
|
||||
adr_rel
|
||||
mov r0, #3
|
||||
b instr_end
|
||||
_07:
|
||||
_b7:
|
||||
_fc:
|
||||
_f7:
|
||||
_c7:
|
||||
_93:
|
||||
b _xx
|
||||
#endif
|
||||
|
||||
// http://emu-docs.org/CPU%2065xx/undocop.txt
|
||||
|
||||
|
|
@ -1455,13 +1664,16 @@ _xx:
|
|||
bic r2, #1
|
||||
str r2, [r3]
|
||||
#endif
|
||||
mov r1, r0
|
||||
unbase_pc reg_pc
|
||||
lsr reg_f, #24
|
||||
stmfd sp!, {r0,reg_f,reg_sp,reg_pc}
|
||||
ldr r0, =unhandled_msg
|
||||
mov r2, reg_a
|
||||
mov r3, reg_x
|
||||
stmfd sp!, {reg_y,reg_sp,reg_pc}
|
||||
mov r1, reg_a
|
||||
mov r2, reg_x
|
||||
mov r3, reg_y
|
||||
bl iprintf
|
||||
k: b k
|
||||
hang:
|
||||
b hang
|
||||
|
||||
// int cpu_run_1 (int cycles_to_do)
|
||||
cpu_run:
|
||||
|
|
@ -1473,39 +1685,38 @@ cpu_run:
|
|||
mov cycles, r0
|
||||
loop:
|
||||
fetch
|
||||
#if 0
|
||||
#ifdef PRINT_TRACE
|
||||
unbase_pc reg_pc
|
||||
mov r3, reg_pc, lsr #12
|
||||
cmp r3, #0xf
|
||||
beq e
|
||||
stmfd sp!, {reg_pc,r0}
|
||||
lsr reg_f, #24
|
||||
stmfd sp!, {r0,reg_f,reg_sp,reg_pc}
|
||||
ldr r0, =debug_msg
|
||||
mov r1, reg_a
|
||||
mov r2, reg_x
|
||||
mov r3, reg_y
|
||||
bl iprintf
|
||||
ldmfd sp!, {reg_pc,r0}
|
||||
e: rebase_pc reg_pc
|
||||
ldmfd sp!, {r0,reg_f,reg_sp,reg_pc}
|
||||
lsl reg_f, #24
|
||||
1: rebase_pc reg_pc
|
||||
#endif
|
||||
ldr pc, [pc, r0, lsl #2]
|
||||
nop
|
||||
op_tab:
|
||||
.word _00,_01,_xx,_xx,_04,_05,_06,_07,_08,_09,_0a,_xx,_xx,_0d,_0e,_xx
|
||||
.word _10,_11,_xx,_xx,_xx,_15,_16,_xx,_18,_19,_xx,_xx,_xx,_1d,_1e,_xx
|
||||
.word _00,_01,_xx,_xx,_04,_05,_06,_07,_08,_09,_0a,_xx,_0c,_0d,_0e,_xx
|
||||
.word _10,_11,_xx,_xx,_xx,_15,_16,_xx,_18,_19,_1a,_xx,_xx,_1d,_1e,_xx
|
||||
.word _20,_21,_xx,_xx,_24,_25,_26,_xx,_28,_29,_2a,_xx,_2c,_2d,_2e,_xx
|
||||
.word _30,_31,_xx,_xx,_xx,_35,_36,_xx,_38,_39,_xx,_xx,_xx,_3d,_3e,_xx
|
||||
.word _30,_31,_xx,_xx,_xx,_35,_36,_xx,_38,_39,_3a,_xx,_3c,_3d,_3e,_xx
|
||||
.word _40,_41,_xx,_xx,_xx,_45,_46,_xx,_48,_49,_4a,_xx,_4c,_4d,_4e,_xx
|
||||
.word _50,_51,_xx,_xx,_xx,_55,_56,_xx,_58,_59,_xx,_xx,_xx,_5d,_5e,_xx
|
||||
.word _60,_61,_xx,_xx,_xx,_65,_66,_xx,_68,_69,_6a,_xx,_6c,_6d,_6e,_xx
|
||||
.word _70,_71,_xx,_xx,_xx,_75,_76,_xx,_78,_79,_7a,_xx,_xx,_7d,_7e,_xx
|
||||
.word _xx,_81,_xx,_xx,_84,_85,_86,_xx,_88,_xx,_8a,_xx,_8c,_8d,_8e,_xx
|
||||
.word _90,_91,_xx,_xx,_94,_95,_96,_xx,_98,_99,_9a,_xx,_xx,_9d,_xx,_xx
|
||||
.word _50,_51,_xx,_xx,_xx,_55,_56,_xx,_58,_59,_5a,_xx,_xx,_5d,_5e,_xx
|
||||
.word _60,_61,_xx,_xx,_64,_65,_66,_xx,_68,_69,_6a,_xx,_6c,_6d,_6e,_xx
|
||||
.word _70,_71,_xx,_xx,_74,_75,_76,_xx,_78,_79,_7a,_xx,_xx,_7d,_7e,_xx
|
||||
.word _80,_81,_xx,_xx,_84,_85,_86,_xx,_88,_89,_8a,_xx,_8c,_8d,_8e,_xx
|
||||
.word _90,_91,_xx,_93,_94,_95,_96,_xx,_98,_99,_9a,_xx,_9c,_9d,_9e,_xx
|
||||
.word _a0,_a1,_a2,_xx,_a4,_a5,_a6,_xx,_a8,_a9,_aa,_xx,_ac,_ad,_ae,_xx
|
||||
.word _b0,_b1,_xx,_xx,_b4,_b5,_b6,_b7,_b8,_b9,_ba,_xx,_bc,_bd,_be,_xx
|
||||
.word _c0,_c1,_xx,_xx,_c4,_c5,_c6,_xx,_c8,_c9,_ca,_xx,_cc,_cd,_ce,_xx
|
||||
.word _d0,_d1,_xx,_xx,_xx,_d5,_d6,_xx,_d8,_d9,_xx,_xx,_xx,_dd,_de,_xx
|
||||
.word _c0,_c1,_xx,_xx,_c4,_c5,_c6,_c7,_c8,_c9,_ca,_xx,_cc,_cd,_ce,_xx
|
||||
.word _d0,_d1,_xx,_xx,_xx,_d5,_d6,_xx,_d8,_d9,_da,_xx,_xx,_dd,_de,_xx
|
||||
.word _e0,_e1,_xx,_xx,_e4,_e5,_e6,_xx,_e8,_e9,_ea,_xx,_ec,_ed,_ee,_xx
|
||||
.word _f0,_f1,_xx,_xx,_xx,_f5,_f6,_xx,_f8,_f9,_xx,_xx,_fc,_fd,_fe,_xx
|
||||
.word _f0,_f1,_xx,_xx,_xx,_f5,_f6,_f7,_f8,_f9,_fa,_xx,_fc,_fd,_fe,_xx
|
||||
instr_end:
|
||||
subs cycles, r0
|
||||
bpl loop
|
||||
|
|
@ -1530,7 +1741,6 @@ cpu_reset:
|
|||
mov r5, r0 // r5 = pc
|
||||
mov r4, #0xfd // r4 = sp
|
||||
rebase_pc r5
|
||||
rebase_sp r4
|
||||
mov r0, #0 // r0 = f
|
||||
mov r1, #0 // r1 = y
|
||||
mov r2, #0 // r2 = x
|
||||
|
|
@ -1544,8 +1754,12 @@ cpu_regs:
|
|||
last_page:
|
||||
.word 0
|
||||
|
||||
.section .rodata
|
||||
unhandled_msg:
|
||||
.ascii "Unhandled op\n"
|
||||
.ascii "- Unhandled op!\n"
|
||||
debug_msg:
|
||||
.ascii "A%02x X%02x Y%02x P%04x OP %02x\n"
|
||||
.ascii "A%02x X%02x Y%02x OP%02x F%02x SP%02x P%04x\n"
|
||||
.byte 0
|
||||
idle_loop_msg:
|
||||
.ascii "Idle %04x\n"
|
||||
.byte 0
|
||||
|
|
|
|||
19
source/emu.c
19
source/emu.c
|
|
@ -9,7 +9,6 @@ void irq_vblank ()
|
|||
if (vblanks++ == 60) {
|
||||
consoleClear();
|
||||
iprintf("FPS %i\n", frames_done);
|
||||
// iprintf("keybd_latch : %02x\n", keybd_latch);
|
||||
frames_done = 0;
|
||||
vblanks = 0;
|
||||
}
|
||||
|
|
@ -27,6 +26,7 @@ int valid_rom_crc (const u16 crc)
|
|||
const u16 known_crcs[] = {
|
||||
0xAC8F, // 12288 BASIC.ROM
|
||||
0x3F44, // 12288 apple.rom
|
||||
0x9CB5, // 12288 A2ROM.BIN
|
||||
};
|
||||
int i;
|
||||
|
||||
|
|
@ -42,14 +42,15 @@ void emu_init ()
|
|||
u16 crc;
|
||||
int valid_crc;
|
||||
|
||||
keyboardShow();
|
||||
keysSetRepeat(30, 10);
|
||||
/*keyboardShow();*/
|
||||
|
||||
// Set some sane defaults
|
||||
emu_vsync = 1;
|
||||
emu_vsync = 0;
|
||||
|
||||
// Setup the video hardware
|
||||
video_init();
|
||||
|
||||
#if 1
|
||||
// Load the appropriate bios
|
||||
if (load_bin("BASIC.ROM", 0xD000, 0x3000, &crc)) {
|
||||
valid_crc = valid_rom_crc(crc);
|
||||
|
|
@ -64,6 +65,16 @@ void emu_init ()
|
|||
|
||||
// Load the disk rom in place
|
||||
load_buf(disk_rom, 0xc600, 0x100);
|
||||
#else
|
||||
if (load_bin("6502_functional_test.bin", 0x0, -1, NULL) > 0) {
|
||||
const u16 reset_patch = 0x0400;
|
||||
iprintf("Test rom loaded\n");
|
||||
iprintf("PC : %04x\n", mainram[0xFFFD]<<8|mainram[0xFFFC]);
|
||||
iprintf("Routing the reset vector to %04x\n", reset_patch);
|
||||
mainram[0xFFFC] = reset_patch&0xFF;
|
||||
mainram[0xFFFD] = (reset_patch>>8)&0xFF;
|
||||
}
|
||||
#endif
|
||||
|
||||
basename = NULL;
|
||||
|
||||
|
|
|
|||
|
|
@ -23,11 +23,13 @@ void update_input ()
|
|||
int kbd_key;
|
||||
|
||||
scanKeys();
|
||||
keys = keysHeld()&0xfff;
|
||||
keys = (keysDownRepeat()|keysDown())&0xfff;
|
||||
|
||||
// Send keyboard scancodes when a key is pressed
|
||||
if (emu_input == INPUT_KBD && keys) {
|
||||
keybd_latch = 0x80 ^ key_map[__builtin_ctz(keys)];
|
||||
int bit_set = __builtin_ffs(keys);
|
||||
if (bit_set)
|
||||
keybd_latch = 0x80 ^ key_map[bit_set-1];
|
||||
}
|
||||
|
||||
if (emu_input == INPUT_JSTK) {
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ int main(int argc, char **argv)
|
|||
keyboardDemoInit();
|
||||
|
||||
fatInitDefault();
|
||||
/*nitroFSInit(NULL);*/
|
||||
nitroFSInit(NULL);
|
||||
|
||||
soundEnable();
|
||||
|
||||
|
|
@ -22,11 +22,12 @@ int main(int argc, char **argv)
|
|||
emu_init();
|
||||
|
||||
if (argc != 2) {
|
||||
/*load_disk("Airheart (1986)(Broderbund)[cr].dsk");*/
|
||||
// Slow loading
|
||||
/*load_disk("PACMAN.DSK");*/
|
||||
/*load_disk("Karateka (1984)(Broderbund).dsk");*/
|
||||
// Awesome!
|
||||
/*load_disk("lode.dsk");*/
|
||||
load_disk("lode.dsk");
|
||||
// AppleII+
|
||||
/*load_disk("Prince of Persia (1989)(Broderbund)(Disk 1 of 3)[cr].dsk");*/
|
||||
// Gfx heavy
|
||||
|
|
@ -36,13 +37,14 @@ int main(int argc, char **argv)
|
|||
/*load_disk("Round About (1983)(Datamost).dsk");*/
|
||||
/*load_disk("Bug Attack (1981)(Cavalier Computer).dsk");*/
|
||||
// Scroller
|
||||
load_disk("TetrisII.DSK");
|
||||
/*load_disk("TetrisII.DSK");*/
|
||||
// Mixed mode
|
||||
/*load_disk("tetris48k.nib");*/
|
||||
// Lowres
|
||||
/*load_disk("Fracas (1980)(Quality Software).dsk");*/
|
||||
/*load_disk("Colorix.dsk");*/
|
||||
/*load_disk("LoRes Games.DSK");*/
|
||||
/*load_disk("LoRes Hijinks.DSK");*/
|
||||
// SP Crash
|
||||
/*load_disk("Apple II Business Graphics 1.0 (1981).nib");*/
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -16,8 +16,8 @@ u8 readb (u16 addr);
|
|||
void writeb (u16 addr, u8 val);
|
||||
void mem_reset (void);
|
||||
|
||||
int load_bin (char *file, u16 addr, u16 len, u16 *crc);
|
||||
int load_buf (const u8 *buf, u16 addr, u16 len);
|
||||
ssize_t load_bin (const char *file, const u32 addr, ssize_t len, u16 *crc);
|
||||
ssize_t load_buf (const u8 *buf, const u32 addr, ssize_t len);
|
||||
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -4,36 +4,48 @@
|
|||
#include "cpu.h"
|
||||
#include "mem.h"
|
||||
|
||||
int load_buf (const u8 *buf, u16 addr, u16 len)
|
||||
ssize_t load_buf (const u8 *buf, const u32 addr, const ssize_t len)
|
||||
{
|
||||
if (addr + len > 0x10000) {
|
||||
iprintf("oob\n");
|
||||
return 0;
|
||||
return -1;
|
||||
}
|
||||
memcpy(mainram + addr, buf, len);
|
||||
|
||||
return 1;
|
||||
return len;
|
||||
}
|
||||
|
||||
int load_bin (char *file, u16 addr, u16 len, u16 *crc)
|
||||
ssize_t load_bin (const char *file, const u32 addr, const ssize_t len, u16 *crc)
|
||||
{
|
||||
FILE *f;
|
||||
size_t read, bin_len;
|
||||
|
||||
if (addr + len > 0x10000) {
|
||||
iprintf("oob\n");
|
||||
return 0;
|
||||
}
|
||||
f = fopen(file, "rb");
|
||||
if (!f) {
|
||||
iprintf("Can't open %s\n", file);
|
||||
return 0;
|
||||
return -1;
|
||||
}
|
||||
fread(mainram + addr, 1, len, f);
|
||||
|
||||
if (len < 0) {
|
||||
fseek(f, 0, SEEK_END);
|
||||
bin_len = ftell(f);
|
||||
fseek(f, 0, SEEK_SET);
|
||||
} else
|
||||
bin_len = len;
|
||||
|
||||
if (addr + bin_len > 0x10000) {
|
||||
bin_len = 0x4000;
|
||||
iprintf("oob\n");
|
||||
fclose(f);
|
||||
return -1;
|
||||
}
|
||||
read = fread(mainram + addr, 1, bin_len, f);
|
||||
fclose(f);
|
||||
iprintf("Read %x to %x\n", read, addr);
|
||||
|
||||
if (crc)
|
||||
*crc = swiCRC16(0xffff, mainram + addr, len);
|
||||
*crc = swiCRC16(0xffff, mainram + addr, read);
|
||||
|
||||
return 1;
|
||||
return read;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -75,17 +75,17 @@ void menu_print_page (const page_t *page, int *opts)
|
|||
if (sel_entry->opts_no) {
|
||||
if (keys&KEY_LEFT && opts[cur] > 0) {
|
||||
opts[cur]--;
|
||||
if (sel_entry->cb) sel_entry->cb(opts[cur]);
|
||||
/*if (sel_entry->cb) sel_entry->cb(opts[cur]);*/
|
||||
}
|
||||
if (keys&KEY_RIGHT && opts[cur] < sel_entry->opts_no - 1) {
|
||||
opts[cur]++;
|
||||
if (sel_entry->cb) sel_entry->cb(opts[cur]);
|
||||
/*if (sel_entry->cb) sel_entry->cb(opts[cur]);*/
|
||||
}
|
||||
}
|
||||
|
||||
if (keys&KEY_A) {
|
||||
if (sel_entry->cb)
|
||||
sel_entry->cb(opts[cur]); // TODO : Handle errors
|
||||
if (sel_entry->cb(opts[cur]))
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -97,4 +97,10 @@ void menu_print_page (const page_t *page, int *opts)
|
|||
}
|
||||
}
|
||||
|
||||
void print_msg (const char *msg)
|
||||
{
|
||||
iprintf("\n-- %s\n", msg);
|
||||
swiDelay(10000000);
|
||||
}
|
||||
|
||||
void pause_menu () { menu_print_page(&paused_pg, (int *)&paused_pg_opt); }
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ typedef struct state_hdr_t {
|
|||
|
||||
#define STATE_MAGIC (0x47525033)
|
||||
|
||||
char *build_path (int slot)
|
||||
char *build_path (const int slot)
|
||||
{
|
||||
static char tmp[1024];
|
||||
if (basename)
|
||||
|
|
@ -21,14 +21,18 @@ char *build_path (int slot)
|
|||
return tmp;
|
||||
}
|
||||
|
||||
int state_save (int slot)
|
||||
int state_save (const int slot)
|
||||
{
|
||||
FILE *f;
|
||||
state_hdr_t h;
|
||||
const char *path;
|
||||
|
||||
f = fopen(build_path(slot), "w+");
|
||||
if (f)
|
||||
path = build_path(slot+1);
|
||||
f = fopen(path, "wb");
|
||||
if (!f) {
|
||||
print_msg("Save failed!");
|
||||
return 0;
|
||||
}
|
||||
|
||||
h.magic = STATE_MAGIC;
|
||||
h.ver = 1;
|
||||
|
|
@ -56,22 +60,27 @@ int state_save (int slot)
|
|||
return 1;
|
||||
}
|
||||
|
||||
int state_load (int slot)
|
||||
int state_load (const int slot)
|
||||
{
|
||||
FILE *f;
|
||||
state_hdr_t h;
|
||||
const char *path;
|
||||
|
||||
f = fopen(build_path(slot), "w+");
|
||||
if (f)
|
||||
path = build_path(slot+1);
|
||||
f = fopen(path, "rb");
|
||||
if (!f) {
|
||||
print_msg("Load failed!");
|
||||
return 0;
|
||||
|
||||
h.magic = STATE_MAGIC;
|
||||
h.ver = 1;
|
||||
h.flags = 0;
|
||||
h.resv = 0;
|
||||
}
|
||||
|
||||
fread(&h, 1, sizeof(state_hdr_t), f);
|
||||
|
||||
if (h.magic != STATE_MAGIC) {
|
||||
fclose(f);
|
||||
print_msg("Invalid save file!");
|
||||
return 0;
|
||||
}
|
||||
|
||||
fread(&cpu_regs, 6, 4, f);
|
||||
fread(&mainram, 1, sizeof(mainram), f);
|
||||
fread(&lcram, 1, sizeof(lcram), f);
|
||||
|
|
|
|||
|
|
@ -112,11 +112,11 @@ u8 video_io_read (u16 addr)
|
|||
switch (addr&0xf) {
|
||||
case 0x0:
|
||||
text_mode = 0;
|
||||
mixed_mode = 0;
|
||||
/*mixed_mode = 0;*/
|
||||
break;
|
||||
case 0x1:
|
||||
text_mode = 1;
|
||||
mixed_mode = 0;
|
||||
/*mixed_mode = 0;*/
|
||||
break;
|
||||
case 0x2:
|
||||
mixed_mode = 0;
|
||||
|
|
@ -132,11 +132,9 @@ u8 video_io_read (u16 addr)
|
|||
break;
|
||||
case 0x6:
|
||||
hires = 0;
|
||||
mixed_mode = 0;
|
||||
break;
|
||||
case 0x7:
|
||||
hires = 1;
|
||||
mixed_mode = 0;
|
||||
break;
|
||||
// Annunciators
|
||||
case 0x8:
|
||||
|
|
@ -176,12 +174,13 @@ void draw_lores_scr (u16 *map)
|
|||
*map++ = col_a << 8 | col_a;
|
||||
*map++ = col_a << 8 | col_a;
|
||||
*map++ = col_a << 8 | col_a;
|
||||
*map++ = col_b << 8 | col_a;
|
||||
*map++ = col_a << 8 | col_a;
|
||||
*map++ = col_b << 8 | col_b;
|
||||
*map++ = col_b << 8 | col_b;
|
||||
*map++ = col_b << 8 | col_b;
|
||||
*map++ = col_b << 8 | col_b;
|
||||
}
|
||||
map += 232/2;
|
||||
map += 192/2;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -320,24 +319,25 @@ void video_draw ()
|
|||
|
||||
int video_set_scale (int mode)
|
||||
{
|
||||
int scale_x;
|
||||
int scaleg_x, scalet_x;
|
||||
int scale_y;
|
||||
|
||||
switch (mode) {
|
||||
default:
|
||||
case 0:
|
||||
scale_x = floatToFixed(1., 8);
|
||||
scaleg_x = scalet_x = floatToFixed(1., 8);
|
||||
scale_y = floatToFixed(1., 8);
|
||||
break;
|
||||
case 1:
|
||||
// 280 / 256 = 1.09
|
||||
scale_x = floatToFixed(1.09, 8);
|
||||
scaleg_x = floatToFixed(1.09, 8);
|
||||
scalet_x = floatToFixed(1.25, 8);
|
||||
scale_y = floatToFixed(1., 8);
|
||||
break;
|
||||
}
|
||||
|
||||
bgSetScale(gfx_bg, scale_x, scale_y);
|
||||
bgSetScale(text_bg, scale_x, scale_y);
|
||||
bgSetScale(gfx_bg, scaleg_x, scale_y);
|
||||
bgSetScale(text_bg, scalet_x, scale_y);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue