izapple2/cardSaturn.go

165 lines
3.0 KiB
Go
Raw Normal View History

2019-05-17 07:54:49 +00:00
package apple2
import (
"encoding/binary"
"io"
)
2019-05-17 07:54:49 +00:00
/*
RAM card with 128Kb. It's like 8 language cards.
http://www.applelogic.org/files/SATURN128MAN.pdf
*/
type cardSaturn struct {
cardBase
readState bool
2019-10-20 22:00:42 +00:00
writeState uint8
altBank bool
2019-10-20 22:00:42 +00:00
activeBlock uint8
2019-05-17 07:54:49 +00:00
}
const (
saturnBlocks = 8
)
2019-05-18 14:43:51 +00:00
func (c *cardSaturn) assign(a *Apple2, slot int) {
2019-05-17 07:54:49 +00:00
c.readState = false
c.writeState = lcWriteEnabled
c.altBank = true
c.activeBlock = 0
a.mmu.initLanguageRAM(saturnBlocks)
2019-05-17 07:54:49 +00:00
2019-10-20 22:00:42 +00:00
for i := uint8(0x0); i <= 0xf; i++ {
2019-05-17 07:54:49 +00:00
iCopy := i
2019-10-20 22:00:42 +00:00
c.addCardSoftSwitchR(iCopy, func(*ioC0Page) uint8 {
c.ssAction(iCopy)
2019-05-17 07:54:49 +00:00
return 0
2019-10-20 22:00:42 +00:00
}, "SATURNR")
c.addCardSoftSwitchW(iCopy, func(*ioC0Page, uint8) {
c.ssAction(iCopy)
2019-10-20 22:00:42 +00:00
}, "SATURNW")
2019-05-17 07:54:49 +00:00
}
2019-05-18 14:43:51 +00:00
c.cardBase.assign(a, slot)
c.applyState()
2019-05-17 07:54:49 +00:00
}
func (c *cardSaturn) ssAction(ss uint8) {
2019-05-17 07:54:49 +00:00
switch ss {
case 0:
// RAM read, no writes
c.altBank = false
2019-05-17 07:54:49 +00:00
c.readState = true
c.writeState = lcWriteDisabled
case 1:
// ROM read, RAM write
c.altBank = false
2019-05-17 07:54:49 +00:00
c.readState = false
c.writeState++
case 2:
// ROM read, no writes
c.altBank = false
2019-05-17 07:54:49 +00:00
c.readState = false
c.writeState = lcWriteDisabled
case 3:
//RAM read, RAM write
c.altBank = false
2019-05-17 07:54:49 +00:00
c.readState = true
c.writeState++
case 4:
c.activeBlock = 0
case 5:
c.activeBlock = 1
case 6:
c.activeBlock = 2
case 7:
c.activeBlock = 3
case 8:
// RAM read, no writes
c.altBank = true
2019-05-17 07:54:49 +00:00
c.readState = true
c.writeState = lcWriteDisabled
case 9:
// ROM read, RAM write
c.altBank = true
2019-05-17 07:54:49 +00:00
c.readState = false
c.writeState++
case 10:
// ROM read, no writes
c.altBank = true
2019-05-17 07:54:49 +00:00
c.readState = false
c.writeState = lcWriteDisabled
case 11:
//RAM read, RAM write
c.altBank = true
2019-05-17 07:54:49 +00:00
c.readState = true
c.writeState++
case 12:
c.activeBlock = 4
2019-05-17 07:54:49 +00:00
case 13:
c.activeBlock = 5
2019-05-17 07:54:49 +00:00
case 14:
c.activeBlock = 6
2019-05-17 07:54:49 +00:00
case 15:
c.activeBlock = 7
2019-05-17 07:54:49 +00:00
}
if c.writeState > lcWriteEnabled {
c.writeState = lcWriteEnabled
}
c.applyState()
}
func (c *cardSaturn) applyState() {
c.a.mmu.setLanguageRAMBlock(c.activeBlock)
c.a.mmu.setLanguageRAM(c.readState, c.writeState == lcWriteEnabled, c.altBank)
}
2019-05-17 07:54:49 +00:00
2019-10-05 23:26:00 +00:00
func (c *cardSaturn) save(w io.Writer) error {
for i := 0; i < saturnBlocks; i++ {
2019-10-05 23:26:00 +00:00
err := binary.Write(w, binary.BigEndian, c.readState)
if err != nil {
return err
}
err = binary.Write(w, binary.BigEndian, c.writeState)
if err != nil {
return err
}
err = binary.Write(w, binary.BigEndian, c.altBank)
2019-10-05 23:26:00 +00:00
if err != nil {
return err
}
err = binary.Write(w, binary.BigEndian, c.activeBlock)
if err != nil {
return err
}
}
2019-10-05 23:26:00 +00:00
return c.cardBase.save(w)
}
2019-10-05 23:26:00 +00:00
func (c *cardSaturn) load(r io.Reader) error {
for i := 0; i < saturnBlocks; i++ {
2019-10-05 23:26:00 +00:00
err := binary.Read(r, binary.BigEndian, &c.readState)
if err != nil {
return err
}
err = binary.Read(r, binary.BigEndian, &c.writeState)
if err != nil {
return err
}
err = binary.Read(r, binary.BigEndian, &c.altBank)
2019-10-05 23:26:00 +00:00
if err != nil {
return err
}
err = binary.Read(r, binary.BigEndian, &c.activeBlock)
if err != nil {
return err
}
c.applyState()
}
2019-10-05 23:26:00 +00:00
return c.cardBase.load(r)
2019-05-17 07:54:49 +00:00
}