mirror of
https://github.com/ivanizag/izapple2.git
synced 2025-01-16 21:32:15 +00:00
More Apple //e softswitches
This commit is contained in:
Ivan Izaguirre
Iván Izaguirre
parent
3660e0ae98
commit
09117fd7c5
@ -8,7 +8,6 @@ import (
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// newApple2 instantiates an apple2
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func newApple2plus() *Apple2 {
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var a Apple2
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a.Name = "Apple ][+"
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a.mmu = newMemoryManager(&a)
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@ -20,12 +19,12 @@ func newApple2plus() *Apple2 {
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}
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func newApple2e() *Apple2 {
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var a Apple2
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a.Name = "Apple IIe"
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a.mmu = newMemoryManager(&a)
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a.cpu = core6502.NewCMOS65c02(a.mmu)
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a.io = newIoC0Page(&a)
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a.mmu.InitRAMalt()
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addApple2SoftSwitches(a.io)
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addApple2ESoftSwitches(a.io)
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@ -33,12 +32,12 @@ func newApple2e() *Apple2 {
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}
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func newApple2eEnhanced() *Apple2 {
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var a Apple2
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a.Name = "Apple //e"
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a.mmu = newMemoryManager(&a)
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a.cpu = core6502.NewCMOS65c02(a.mmu)
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a.io = newIoC0Page(&a)
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a.mmu.InitRAMalt()
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addApple2SoftSwitches(a.io)
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addApple2ESoftSwitches(a.io)
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@ -90,7 +90,7 @@ func MainApple() *Apple2 {
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)
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model := flag.String(
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"model",
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"2e",
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"2enh",
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"set base model. Models available 2plus, 2e, 2enh, base64a",
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)
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profile := flag.Bool(
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@ -1,8 +1,6 @@
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package main
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import (
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"fmt"
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"github.com/veandco/go-sdl2/sdl"
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)
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@ -98,7 +96,6 @@ func (j *sdlJoysticks) ReadButton(i int) bool {
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case 2:
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value = j.button[3] || j.keys[2]
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}
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fmt.Printf("Button %v: %v.\n", i, value)
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return value
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}
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65
base64a.go
65
base64a.go
@ -1,6 +1,8 @@
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package apple2
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import (
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"fmt"
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"github.com/ivanizag/apple2/core6502"
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)
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@ -22,6 +24,45 @@ func newBase64a() *Apple2 {
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return &a
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}
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const (
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// There are 6 ROM chips. Each can have 4Kb or 8Kb. They can fill
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// 2 or 4 banks with 2kb windows.
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base64aRomBankSize = 12 * 1024
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base64aRomBankCount = 4
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base64aRomWindowSize = 2 * 1024
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base64aRomChipCount = 6
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)
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func loadBase64aRom(a *Apple2) error {
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// Load the 6 PROM dumps
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romBanksBytes := make([][]uint8, base64aRomBankCount)
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for j := range romBanksBytes {
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romBanksBytes[j] = make([]uint8, 0, base64aRomBankSize)
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}
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for i := 0; i < base64aRomChipCount; i++ {
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filename := fmt.Sprintf("<internal>/BASE64A_%X.BIN", 0xd0+i*0x08)
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data, err := loadResource(filename)
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if err != nil {
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return err
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}
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for j := range romBanksBytes {
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start := (j * base64aRomWindowSize) % len(data)
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romBanksBytes[j] = append(romBanksBytes[j], data[start:start+base64aRomWindowSize]...)
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}
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}
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// Create banks
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for j := range romBanksBytes {
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a.mmu.physicalROM[j] = newMemoryRange(0xd000, romBanksBytes[j])
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}
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// Start with first bank active
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a.mmu.setActiveROMPage(0)
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return nil
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}
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func addBase64aSoftSwitches(io *ioC0Page) {
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// Other softswitches, not implemented but called from the ROM
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io.addSoftSwitchW(0x0C, notImplementedSoftSwitchW, "80COLOFF")
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@ -32,6 +73,30 @@ func addBase64aSoftSwitches(io *ioC0Page) {
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io.addSoftSwitchW(0x30, func(io *ioC0Page, value uint8) {
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speakerSoftSwitch(io)
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}, "SPEAKER")
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// ROM pagination softswitches. They use the annunciator 0 and 1
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mmu := io.apple2.mmu
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io.addSoftSwitchRW(0x58, func(*ioC0Page) uint8 {
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p := mmu.getActiveROMPage()
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mmu.setActiveROMPage(p & 2)
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return 0
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}, "ANN0OFF-ROM")
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io.addSoftSwitchRW(0x59, func(*ioC0Page) uint8 {
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p := mmu.getActiveROMPage()
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mmu.setActiveROMPage(p | 1)
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return 0
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}, "ANN0ON-ROM")
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io.addSoftSwitchRW(0x5A, func(*ioC0Page) uint8 {
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p := mmu.getActiveROMPage()
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mmu.setActiveROMPage(p & 1)
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return 0
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}, "ANN1OFF-ROM")
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io.addSoftSwitchRW(0x5B, func(*ioC0Page) uint8 {
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p := mmu.getActiveROMPage()
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mmu.setActiveROMPage(p | 2)
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return 0
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}, "ANN1ON-ROM")
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}
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func charGenColumnsMapBase64a(column int) int {
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@ -1,70 +0,0 @@
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package apple2
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import (
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"fmt"
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)
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/*
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Copam BASE64A uses paginated ROM
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*/
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const (
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// There are 6 ROM chips. Each can have 4Kb or 8Kb. They can fill
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// 2 or 4 banks with 2kb windows.
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base64aRomBankSize = 12 * 1024
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base64aRomBankCount = 4
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base64aRomWindowSize = 2 * 1024
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base64aRomChipCount = 6
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)
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func loadBase64aRom(a *Apple2) error {
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// Load the 6 PROM dumps
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romBanksBytes := make([][]uint8, base64aRomBankCount)
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for j := range romBanksBytes {
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romBanksBytes[j] = make([]uint8, 0, base64aRomBankSize)
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}
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for i := 0; i < base64aRomChipCount; i++ {
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filename := fmt.Sprintf("<internal>/BASE64A_%X.BIN", 0xd0+i*0x08)
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data, err := loadResource(filename)
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if err != nil {
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return err
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}
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for j := range romBanksBytes {
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start := (j * base64aRomWindowSize) % len(data)
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romBanksBytes[j] = append(romBanksBytes[j], data[start:start+base64aRomWindowSize]...)
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}
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}
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// Create banks
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for j := range romBanksBytes {
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a.mmu.physicalROM[j] = newMemoryRange(0xd000, romBanksBytes[j])
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}
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// Start with first bank active
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a.mmu.setActiveROMPage(0)
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// Add rom soft switches. They use the annunciator 0 and 1
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a.io.addSoftSwitchRW(0x58, func(*ioC0Page) uint8 {
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p := a.mmu.getActiveROMPage()
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a.mmu.setActiveROMPage(p & 2)
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return 0
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}, "ANN0OFF-ROM")
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a.io.addSoftSwitchRW(0x59, func(*ioC0Page) uint8 {
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p := a.mmu.getActiveROMPage()
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a.mmu.setActiveROMPage(p | 1)
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return 0
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}, "ANN0ON-ROM")
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a.io.addSoftSwitchRW(0x5A, func(*ioC0Page) uint8 {
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p := a.mmu.getActiveROMPage()
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a.mmu.setActiveROMPage(p & 1)
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return 0
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}, "ANN1OFF-ROM")
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a.io.addSoftSwitchRW(0x5B, func(*ioC0Page) uint8 {
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p := a.mmu.getActiveROMPage()
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a.mmu.setActiveROMPage(p | 2)
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return 0
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}, "ANN1ON-ROM")
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return nil
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}
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@ -47,8 +47,12 @@ func (c *cardLanguage) assign(a *Apple2, slot int) {
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c.writeState = lcWriteEnabled
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c.altBank = true
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a.mmu.initLanguageRAM(1)
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if a.isApple2e {
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// The Apple //e with 128kb has two blocks of language upper RAM
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a.mmu.initLanguageRAM(2)
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} else {
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a.mmu.initLanguageRAM(1)
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}
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for i := uint8(0x0); i <= 0xf; i++ {
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iCopy := i
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c.addCardSoftSwitchR(iCopy, func(*ioC0Page) uint8 {
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@ -2,7 +2,6 @@ package apple2
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import (
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"encoding/binary"
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"fmt"
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"io"
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)
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@ -27,23 +26,27 @@ type memoryManager struct {
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physicalDAltRAM []memoryHandler // 0xd000 to 0xdfff, 4KB. Up to 8 banks.
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physicalEFRAM []memoryHandler // 0xe000 to 0xffff, 8KB. Up to 8 banks.
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// Pages prapared for optional card ROM banks in 0xc800 to 0xcfff
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altMainRAMActiveRead bool // Use extra RAM on the 128KB Apple2e for read
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altMainRAMActiveWrite bool // Use extra RAM on the 128KB Apple2e for write
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c3ROMActive bool // Apple2e slot 3 ROM shadow
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cxROMActive bool // Apple2e slots ROM shadow
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activeSlot uint8 // Active slot owner of 0xc800 to 0xcfff
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// Configuration switches, Language cards
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lcSelectedBlock uint8 // Language card block selected. Usually, allways 0. But Saturn has 8
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lcActiveRead bool // Upper RAM active for read
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lcActiveWrite bool // Upper RAM active for read
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lcAltBank bool // Alternate
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romPage uint8 // Active ROM page
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// Configuration switches, Apple //e
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altZeroPage bool // Use extra RAM from 0x0000 to 0x01ff. And additional language card block
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altMainRAMActiveRead bool // Use extra RAM from 0x0200 to 0xbfff for read
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altMainRAMActiveWrite bool // Use extra RAM from 0x0200 to 0xbfff for write
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c3ROMActive bool // Apple2e slot 3 ROM shadow
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cxROMActive bool // Apple2e slots ROM shadow
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activeSlot uint8 // Active slot owner of 0xc800 to 0xcfff
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// Configuration switches, Base64A
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romPage uint8 // Active ROM page
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}
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const (
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ioC8Off uint16 = 0xcfff
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addressLimitZero uint16 = 0x01ff
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addressLimitMainRAM uint16 = 0xbfff
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addressLimitIO uint16 = 0xc0ff
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addressLimitSlots uint16 = 0xc7ff
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@ -59,14 +62,20 @@ type memoryHandler interface {
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func newMemoryManager(a *Apple2) *memoryManager {
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var mmu memoryManager
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mmu.apple2 = a
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ram := make([]uint8, 0xc000) // Reserve 48kb
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mmu.physicalMainRAM = newMemoryRange(0, ram)
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mmu.physicalMainRAM = newMemoryRange(0, make([]uint8, 0xc000))
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return &mmu
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}
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func (mmu *memoryManager) accessRead(address uint16) memoryHandler {
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// First two pages
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if address <= addressLimitZero {
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if mmu.altZeroPage {
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return mmu.physicalMainRAMAlt
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}
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return mmu.physicalMainRAM
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}
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// Main RAM area
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if address <= addressLimitMainRAM {
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if mmu.altMainRAMActiveRead {
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@ -104,13 +113,17 @@ func (mmu *memoryManager) accessRead(address uint16) memoryHandler {
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// Upper address area
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if mmu.lcActiveRead {
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block := mmu.lcSelectedBlock
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if mmu.altZeroPage {
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block = 1
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}
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if address <= addressLimitDArea {
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if mmu.lcAltBank {
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return mmu.physicalDAltRAM[mmu.lcSelectedBlock]
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return mmu.physicalDAltRAM[block]
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}
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return mmu.physicalDRAM[mmu.lcSelectedBlock]
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return mmu.physicalDRAM[block]
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}
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return mmu.physicalEFRAM[mmu.lcSelectedBlock]
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return mmu.physicalEFRAM[block]
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}
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// Use ROM
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@ -118,6 +131,14 @@ func (mmu *memoryManager) accessRead(address uint16) memoryHandler {
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}
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func (mmu *memoryManager) accessWrite(address uint16) memoryHandler {
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// First two pages
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if address <= addressLimitZero {
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if mmu.altZeroPage {
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return mmu.physicalMainRAMAlt
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}
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return mmu.physicalMainRAM
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}
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// Main RAM area
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if address <= addressLimitMainRAM {
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if mmu.altMainRAMActiveWrite {
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@ -149,13 +170,17 @@ func (mmu *memoryManager) accessWrite(address uint16) memoryHandler {
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// Upper address area
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if mmu.lcActiveWrite {
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block := mmu.lcSelectedBlock
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if mmu.altZeroPage {
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block = 1
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}
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if address <= addressLimitDArea {
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if mmu.lcAltBank {
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return mmu.physicalDAltRAM[mmu.lcSelectedBlock]
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return mmu.physicalDAltRAM[block]
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}
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return mmu.physicalDRAM[mmu.lcSelectedBlock]
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return mmu.physicalDRAM[block]
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}
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return mmu.physicalEFRAM[mmu.lcSelectedBlock]
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return mmu.physicalEFRAM[block]
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}
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// Use ROM
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@ -166,7 +191,7 @@ func (mmu *memoryManager) accessWrite(address uint16) memoryHandler {
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func (mmu *memoryManager) Peek(address uint16) uint8 {
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mh := mmu.accessRead(address)
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if mh == nil {
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fmt.Printf("Reading void addressing 0x%x\n", address)
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//fmt.Printf("Reading void addressing 0x%x\n", address)
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return 0xf4 // Or some random number
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}
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return mh.peek(address)
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@ -176,7 +201,7 @@ func (mmu *memoryManager) Peek(address uint16) uint8 {
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func (mmu *memoryManager) Poke(address uint16, value uint8) {
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mh := mmu.accessWrite(address)
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if mh == nil {
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fmt.Printf("Writing to void addressing 0x%x\n", address)
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//fmt.Printf("Writing to void addressing 0x%x\n", address)
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return
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}
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mh.poke(address, value)
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@ -202,6 +227,10 @@ func (mmu *memoryManager) initLanguageRAM(groups int) {
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}
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}
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func (mmu *memoryManager) InitRAMalt() {
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mmu.physicalMainRAMAlt = newMemoryRange(0, make([]uint8, 0xc000))
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}
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// Memory configuration
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func (mmu *memoryManager) setActiveROMPage(page uint8) {
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mmu.romPage = page
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@ -6,38 +6,25 @@ package apple2
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*/
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const (
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ioFlagRamRd uint8 = 0x13
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ioFlagRamWrt uint8 = 0x14
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ioFlagIntCxRom uint8 = 0x15
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ioFlagAltZp uint8 = 0x16
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ioFlagSlotC3Rom uint8 = 0x17
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ioFlag80Store uint8 = 0x18
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ioFlagAltChar uint8 = 0x1E
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ioFlag80Col uint8 = 0x1F
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ioFlag80Store uint8 = 0x18
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ioFlagAltChar uint8 = 0x1E
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ioFlag80Col uint8 = 0x1F
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// ??? ioVertBlank uin8 = 0x19
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)
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func addApple2ESoftSwitches(io *ioC0Page) {
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// New MMU read softswithes
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io.addSoftSwitchW(0x02, getSoftSwitchExt(ioFlagRamRd, ssOff, nil), "RAMRDOFF")
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io.addSoftSwitchW(0x03, getSoftSwitchExt(ioFlagRamWrt, ssOn, nil), "RAMRDON")
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io.addSoftSwitchR(0x13, getStatusSoftSwitch(ioFlagRamWrt), "RAMRD")
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mmu := io.apple2.mmu
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addSoftSwitchesMmu(io, 0x02, 0x03, 0x13, &mmu.altMainRAMActiveRead, "RAMRD")
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addSoftSwitchesMmu(io, 0x04, 0x05, 0x14, &mmu.altMainRAMActiveWrite, "RAMWRT")
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addSoftSwitchesMmu(io, 0x06, 0x07, 0x15, &mmu.cxROMActive, "INTCXROM")
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addSoftSwitchesMmu(io, 0x08, 0x09, 0x16, &mmu.altZeroPage, "ALTZP")
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addSoftSwitchesMmu(io, 0x0a, 0x0b, 0x17, &mmu.c3ROMActive, "SLOTC3ROM")
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io.addSoftSwitchW(0x04, getSoftSwitchExt(ioFlagRamWrt, ssOff, nil), "RAMWRTOFF")
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io.addSoftSwitchW(0x05, getSoftSwitchExt(ioFlagRamWrt, ssOn, nil), "RAMWRTON")
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io.addSoftSwitchR(0x14, getStatusSoftSwitch(ioFlagRamWrt), "RAMWRT")
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io.addSoftSwitchW(0x06, getSoftSwitchExt(ioFlagIntCxRom, ssOff, softSwitchIntCxRomOff), "INTCXROMOFF")
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io.addSoftSwitchW(0x07, getSoftSwitchExt(ioFlagIntCxRom, ssOn, softSwitchIntCxRomOn), "INTCXROMON")
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io.addSoftSwitchR(0x15, getStatusSoftSwitch(ioFlagIntCxRom), "INTCXROM")
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io.addSoftSwitchW(0x08, getSoftSwitchExt(ioFlagAltZp, ssOff, nil), "ALTZPOFF")
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io.addSoftSwitchW(0x09, getSoftSwitchExt(ioFlagAltZp, ssOn, nil), "ALTZPON")
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io.addSoftSwitchR(0x16, getStatusSoftSwitch(ioFlagAltZp), "ALTZP")
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io.addSoftSwitchW(0x0A, getSoftSwitchExt(ioFlagSlotC3Rom, ssOff, softSwitchSlotC3RomOff), "SLOTC3ROMOFF")
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io.addSoftSwitchW(0x0B, getSoftSwitchExt(ioFlagSlotC3Rom, ssOn, softSwitchSlotC3RomOn), "SLOTC3ROMON")
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io.addSoftSwitchR(0x17, getStatusSoftSwitch(ioFlagSlotC3Rom), "SLOTC3ROM")
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// New IOU read softswithes
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addSoftSwitchesIou(io, 0x00, 0x01, 0x18, ioFlag80Store, "80STORE")
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addSoftSwitchesIou(io, 0x0c, 0x0d, 0x1f, ioFlag80Col, "80COL")
|
||||
addSoftSwitchesIou(io, 0x0e, 0x0f, 0x1e, ioFlagAltChar, "ALTCHARSET")
|
||||
|
||||
// Previous read softswithes
|
||||
io.addSoftSwitchR(0x1A, getStatusSoftSwitch(ioFlagText), "TEXT")
|
||||
@ -45,19 +32,6 @@ func addApple2ESoftSwitches(io *ioC0Page) {
|
||||
io.addSoftSwitchR(0x1C, getStatusSoftSwitch(ioFlagSecondPage), "PAGE2")
|
||||
io.addSoftSwitchR(0x1D, getStatusSoftSwitch(ioFlagHiRes), "HIRES")
|
||||
|
||||
// New IOU read softswithes
|
||||
io.addSoftSwitchW(0x00, getSoftSwitchExt(ioFlag80Store, ssOff, nil), "80STOREOFF")
|
||||
io.addSoftSwitchW(0x01, getSoftSwitchExt(ioFlag80Store, ssOn, nil), "80STOREON")
|
||||
io.addSoftSwitchR(0x18, getStatusSoftSwitch(ioFlag80Store), "80STORE")
|
||||
|
||||
io.addSoftSwitchW(0x0C, getSoftSwitchExt(ioFlag80Col, ssOff, nil), "80COLOFF")
|
||||
io.addSoftSwitchW(0x0D, getSoftSwitchExt(ioFlag80Col, ssOn, nil), "80COLON")
|
||||
io.addSoftSwitchR(0x1F, getStatusSoftSwitch(ioFlag80Col), "80COL")
|
||||
|
||||
io.addSoftSwitchW(0x0E, getSoftSwitchExt(ioFlagAltChar, ssOff, nil), "ALTCHARSETOFF")
|
||||
io.addSoftSwitchW(0x0F, getSoftSwitchExt(ioFlagAltChar, ssOn, nil), "ALTCHARSETON")
|
||||
io.addSoftSwitchR(0x1E, getStatusSoftSwitch(ioFlagAltChar), "ALTCHARSET")
|
||||
|
||||
// TOOD:
|
||||
// AKD read on 0x10
|
||||
// VBL read on 0x19
|
||||
@ -66,37 +40,33 @@ func addApple2ESoftSwitches(io *ioC0Page) {
|
||||
|
||||
}
|
||||
|
||||
type softSwitchExtAction func(io *ioC0Page)
|
||||
func addSoftSwitchesMmu(io *ioC0Page, addressClear uint8, addressSet uint8, AddressGet uint8, flag *bool, name string) {
|
||||
io.addSoftSwitchW(addressClear, func(_ *ioC0Page, _ uint8) {
|
||||
*flag = false
|
||||
}, name+"OFF")
|
||||
|
||||
func getSoftSwitchExt(ioFlag uint8, dstValue uint8, action softSwitchExtAction) softSwitchW {
|
||||
return func(io *ioC0Page, _ uint8) {
|
||||
currentValue := io.softSwitchesData[ioFlag]
|
||||
if currentValue == dstValue {
|
||||
return // Already switched, ignore
|
||||
io.addSoftSwitchW(addressSet, func(_ *ioC0Page, _ uint8) {
|
||||
*flag = true
|
||||
}, name+"ON")
|
||||
|
||||
io.addSoftSwitchR(AddressGet, func(_ *ioC0Page) uint8 {
|
||||
if *flag {
|
||||
return ssOn
|
||||
}
|
||||
if action != nil {
|
||||
action(io)
|
||||
}
|
||||
io.softSwitchesData[ioFlag] = dstValue
|
||||
}
|
||||
return ssOff
|
||||
}, name)
|
||||
}
|
||||
|
||||
func softSwitchIntCxRomOn(io *ioC0Page) {
|
||||
//io.apple2.mmu.setPagesRead(0xc1, 0xcf, io.apple2.mmu.physicalROMe)
|
||||
}
|
||||
func addSoftSwitchesIou(io *ioC0Page, addressClear uint8, addressSet uint8, AddressGet uint8, ioFlag uint8, name string) {
|
||||
io.addSoftSwitchW(addressClear, func(_ *ioC0Page, _ uint8) {
|
||||
io.softSwitchesData[ioFlag] = ssOff
|
||||
}, name+"OFF")
|
||||
|
||||
func softSwitchIntCxRomOff(io *ioC0Page) {
|
||||
// TODO restore all the ROM from the slots for 0xc1 to 0xc7
|
||||
//io.apple2.mmu.setPages(0xc1, 0xc7, nil)
|
||||
}
|
||||
io.addSoftSwitchW(addressSet, func(_ *ioC0Page, _ uint8) {
|
||||
io.softSwitchesData[ioFlag] = ssOn
|
||||
}, name+"ON")
|
||||
|
||||
func softSwitchSlotC3RomOn(io *ioC0Page) {
|
||||
// TODO restore the slot 3 ROM
|
||||
//io.apple2.mmu.setPages(0xc3, 0xc3, nil)
|
||||
io.addSoftSwitchR(AddressGet, func(_ *ioC0Page) uint8 {
|
||||
return io.softSwitchesData[ioFlag]
|
||||
}, name)
|
||||
}
|
||||
|
||||
func softSwitchSlotC3RomOff(io *ioC0Page) {
|
||||
//io.apple2.mmu.setPagesRead(0xc3, 0xc3, io.apple2.mmu.physicalROMe)
|
||||
}
|
||||
|
||||
// TODO: apply state after persistance load
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user