From 0bf4a056061b5198d13f2e3cdf8f935917223bda Mon Sep 17 00:00:00 2001 From: Ivan Izaguirre Date: Wed, 7 Oct 2020 09:37:13 +0200 Subject: [PATCH] Fix warnings --- apple2.go | 2 +- apple2main.go | 2 +- cardDisk2.go | 8 +- cardLanguage.go | 2 +- core6502/cmos65c02.go | 164 ++++++++++---------- core6502/nmos6502.go | 308 ++++++++++++++++++------------------- go.sum | 2 + izapple2sdl/sdlKeyboard.go | 3 +- screen.go | 2 +- traceProDOS.go | 2 +- 10 files changed, 249 insertions(+), 246 deletions(-) diff --git a/apple2.go b/apple2.go index d54863a..bc3d62e 100644 --- a/apple2.go +++ b/apple2.go @@ -128,7 +128,7 @@ const ( CommandShowSpeed // CommandToggleColor toggles between NTSC color TV and Green phospor monitor CommandToggleColor - // CommandDumpDebugInfo dumps usefull info + // CommandDumpDebugInfo dumps useful info CommandDumpDebugInfo // CommandNextCharGenPage cycles the CharGen page if several CommandNextCharGenPage diff --git a/apple2main.go b/apple2main.go index 8995a72..09155b5 100644 --- a/apple2main.go +++ b/apple2main.go @@ -7,7 +7,7 @@ import ( const defaultInternal = "" -// MainApple is a device independant main. Video, keyboard and speaker won't be defined +// MainApple is a device independent main. Video, keyboard and speaker won't be defined func MainApple() *Apple2 { romFile := flag.String( "rom", diff --git a/cardDisk2.go b/cardDisk2.go index a2f12fe..01faf0e 100644 --- a/cardDisk2.go +++ b/cardDisk2.go @@ -173,10 +173,10 @@ line of groups of magnets, each group on the same configuration. We call phase e magnets. The cog is attracted to the enabled magnets, and can stay aligned to a magnet or between two. -Phases (magents): 3 2 1 0 3 2 1 0 3 2 1 0 -Cog direction (step withn a group): 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 +Phases (magnets): 3 2 1 0 3 2 1 0 3 2 1 0 +Cog direction (step within a group): 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 -We will consider that the cog would go to the prefferred postion if there is one. Independenly +We will consider that the cog would go to the prefferred position if there is one. Independently of the previous position. The previous position is only used to know if it goes up or down a full group. */ @@ -231,7 +231,7 @@ func moveStep(phases uint8, prevStep int) int { nextStep = maxStep } } else if delta == 4 { - // Don't move if magnets push on the oposite direction + // Don't move if magnets push on the opposite direction nextStep = prevStep } else { // delta > 4 // Steps down diff --git a/cardLanguage.go b/cardLanguage.go index 6cd3e9d..d779cf2 100644 --- a/cardLanguage.go +++ b/cardLanguage.go @@ -11,7 +11,7 @@ Note also that language cards for the Apple ][ had ROM on board to replace the main board F8 ROM with Autostart. That was not used/needed on the Apple ][+. As this emulates the Apple ][+, it is not considered. For the Plus it is often -refered as Language card but it is really a 16 KB Ram card, +referred as Language card but it is really a 16 KB Ram card, "When RAM is deselected, the ROM on the Language card is selected for diff --git a/core6502/cmos65c02.go b/core6502/cmos65c02.go index 075bf6b..31c370e 100644 --- a/core6502/cmos65c02.go +++ b/core6502/cmos65c02.go @@ -64,105 +64,105 @@ func add65c02NOPs(opcodes *[256]opcode) { var opcodes65c02Delta = [256]opcode{ // Functional difference - 0x00: opcode{"BRK", 1, 7, modeImplicit, opBRKAlt}, - 0x24: opcode{"BIT", 2, 3, modeZeroPage, opBIT}, - 0x2C: opcode{"BIT", 3, 3, modeAbsolute, opBIT}, + 0x00: {"BRK", 1, 7, modeImplicit, opBRKAlt}, + 0x24: {"BIT", 2, 3, modeZeroPage, opBIT}, + 0x2C: {"BIT", 3, 3, modeAbsolute, opBIT}, // Fixed BCD arithmetic flags - 0x69: opcode{"ADC", 2, 2, modeImmediate, opADCAlt}, - 0x65: opcode{"ADC", 2, 3, modeZeroPage, opADCAlt}, - 0x75: opcode{"ADC", 2, 4, modeZeroPageX, opADCAlt}, - 0x6D: opcode{"ADC", 3, 4, modeAbsolute, opADCAlt}, - 0x7D: opcode{"ADC", 3, 4, modeAbsoluteX, opADCAlt}, - 0x79: opcode{"ADC", 3, 4, modeAbsoluteY, opADCAlt}, - 0x61: opcode{"ADC", 2, 6, modeIndexedIndirectX, opADCAlt}, - 0x71: opcode{"ADC", 2, 5, modeIndirectIndexedY, opADCAlt}, - 0xE9: opcode{"SBC", 2, 2, modeImmediate, opSBCAlt}, - 0xE5: opcode{"SBC", 2, 3, modeZeroPage, opSBCAlt}, - 0xF5: opcode{"SBC", 2, 4, modeZeroPageX, opSBCAlt}, - 0xED: opcode{"SBC", 3, 4, modeAbsolute, opSBCAlt}, - 0xFD: opcode{"SBC", 3, 4, modeAbsoluteX, opSBCAlt}, - 0xF9: opcode{"SBC", 3, 4, modeAbsoluteY, opSBCAlt}, - 0xE1: opcode{"SBC", 2, 6, modeIndexedIndirectX, opSBCAlt}, - 0xF1: opcode{"SBC", 2, 5, modeIndirectIndexedY, opSBCAlt}, + 0x69: {"ADC", 2, 2, modeImmediate, opADCAlt}, + 0x65: {"ADC", 2, 3, modeZeroPage, opADCAlt}, + 0x75: {"ADC", 2, 4, modeZeroPageX, opADCAlt}, + 0x6D: {"ADC", 3, 4, modeAbsolute, opADCAlt}, + 0x7D: {"ADC", 3, 4, modeAbsoluteX, opADCAlt}, + 0x79: {"ADC", 3, 4, modeAbsoluteY, opADCAlt}, + 0x61: {"ADC", 2, 6, modeIndexedIndirectX, opADCAlt}, + 0x71: {"ADC", 2, 5, modeIndirectIndexedY, opADCAlt}, + 0xE9: {"SBC", 2, 2, modeImmediate, opSBCAlt}, + 0xE5: {"SBC", 2, 3, modeZeroPage, opSBCAlt}, + 0xF5: {"SBC", 2, 4, modeZeroPageX, opSBCAlt}, + 0xED: {"SBC", 3, 4, modeAbsolute, opSBCAlt}, + 0xFD: {"SBC", 3, 4, modeAbsoluteX, opSBCAlt}, + 0xF9: {"SBC", 3, 4, modeAbsoluteY, opSBCAlt}, + 0xE1: {"SBC", 2, 6, modeIndexedIndirectX, opSBCAlt}, + 0xF1: {"SBC", 2, 5, modeIndirectIndexedY, opSBCAlt}, // Different cycle count - 0x1e: opcode{"ASL", 3, 6, modeAbsoluteX, buildOpShift(true, false)}, - 0x3e: opcode{"ROL", 3, 6, modeAbsoluteX, buildOpShift(true, true)}, - 0x5e: opcode{"LSR", 3, 6, modeAbsoluteX, buildOpShift(false, false)}, - 0x7e: opcode{"ROR", 3, 6, modeAbsoluteX, buildOpShift(false, true)}, + 0x1e: {"ASL", 3, 6, modeAbsoluteX, buildOpShift(true, false)}, + 0x3e: {"ROL", 3, 6, modeAbsoluteX, buildOpShift(true, true)}, + 0x5e: {"LSR", 3, 6, modeAbsoluteX, buildOpShift(false, false)}, + 0x7e: {"ROR", 3, 6, modeAbsoluteX, buildOpShift(false, true)}, // New indirect zero page addresssing mode - 0x12: opcode{"ORA", 2, 5, modeIndirectZeroPage, buildOpLogic(operationOr)}, - 0x32: opcode{"AND", 2, 5, modeIndirectZeroPage, buildOpLogic(operationAnd)}, - 0x52: opcode{"EOR", 2, 5, modeIndirectZeroPage, buildOpLogic(operationXor)}, - 0x72: opcode{"ADC", 2, 5, modeIndirectZeroPage, opADCAlt}, - 0x92: opcode{"STA", 2, 5, modeIndirectZeroPage, buildOpStore(regA)}, - 0xb2: opcode{"LDA", 2, 5, modeIndirectZeroPage, buildOpLoad(regA)}, - 0xd2: opcode{"CMP", 2, 5, modeIndirectZeroPage, buildOpCompare(regA)}, - 0xf2: opcode{"SBC", 2, 5, modeIndirectZeroPage, opSBCAlt}, + 0x12: {"ORA", 2, 5, modeIndirectZeroPage, buildOpLogic(operationOr)}, + 0x32: {"AND", 2, 5, modeIndirectZeroPage, buildOpLogic(operationAnd)}, + 0x52: {"EOR", 2, 5, modeIndirectZeroPage, buildOpLogic(operationXor)}, + 0x72: {"ADC", 2, 5, modeIndirectZeroPage, opADCAlt}, + 0x92: {"STA", 2, 5, modeIndirectZeroPage, buildOpStore(regA)}, + 0xb2: {"LDA", 2, 5, modeIndirectZeroPage, buildOpLoad(regA)}, + 0xd2: {"CMP", 2, 5, modeIndirectZeroPage, buildOpCompare(regA)}, + 0xf2: {"SBC", 2, 5, modeIndirectZeroPage, opSBCAlt}, // New addressing options - 0x89: opcode{"BIT", 2, 2, modeImmediate, opBIT}, - 0x34: opcode{"BIT", 2, 4, modeZeroPageX, opBIT}, - 0x3c: opcode{"BIT", 3, 4, modeAbsoluteX, opBIT}, - 0x1a: opcode{"INC", 1, 2, modeAccumulator, buildOpIncDec(true)}, - 0x3a: opcode{"DEC", 1, 2, modeAccumulator, buildOpIncDec(false)}, - 0x7c: opcode{"JMP", 3, 6, modeAbsoluteIndexedIndirectX, opJMP}, + 0x89: {"BIT", 2, 2, modeImmediate, opBIT}, + 0x34: {"BIT", 2, 4, modeZeroPageX, opBIT}, + 0x3c: {"BIT", 3, 4, modeAbsoluteX, opBIT}, + 0x1a: {"INC", 1, 2, modeAccumulator, buildOpIncDec(true)}, + 0x3a: {"DEC", 1, 2, modeAccumulator, buildOpIncDec(false)}, + 0x7c: {"JMP", 3, 6, modeAbsoluteIndexedIndirectX, opJMP}, // Additional instructions: BRA, PHX, PHY, PLX, PLY, STZ, TRB, TSB - 0xda: opcode{"PHX", 1, 3, modeImplicit, buildOpPush(regX)}, - 0x5a: opcode{"PHY", 1, 3, modeImplicit, buildOpPush(regY)}, - 0xfa: opcode{"PLX", 1, 4, modeImplicit, buildOpPull(regX)}, - 0x7a: opcode{"PLY", 1, 4, modeImplicit, buildOpPull(regY)}, - 0x80: opcode{"BRA", 2, 4, modeRelative, opJMP}, + 0xda: {"PHX", 1, 3, modeImplicit, buildOpPush(regX)}, + 0x5a: {"PHY", 1, 3, modeImplicit, buildOpPush(regY)}, + 0xfa: {"PLX", 1, 4, modeImplicit, buildOpPull(regX)}, + 0x7a: {"PLY", 1, 4, modeImplicit, buildOpPull(regY)}, + 0x80: {"BRA", 2, 4, modeRelative, opJMP}, - 0x64: opcode{"STZ", 2, 3, modeZeroPage, opSTZ}, - 0x74: opcode{"STZ", 2, 4, modeZeroPageX, opSTZ}, - 0x9c: opcode{"STZ", 3, 4, modeAbsolute, opSTZ}, - 0x9e: opcode{"STZ", 3, 5, modeAbsoluteX, opSTZ}, + 0x64: {"STZ", 2, 3, modeZeroPage, opSTZ}, + 0x74: {"STZ", 2, 4, modeZeroPageX, opSTZ}, + 0x9c: {"STZ", 3, 4, modeAbsolute, opSTZ}, + 0x9e: {"STZ", 3, 5, modeAbsoluteX, opSTZ}, - 0x14: opcode{"TRB", 2, 5, modeZeroPage, opTRB}, - 0x1c: opcode{"TRB", 3, 6, modeAbsolute, opTRB}, + 0x14: {"TRB", 2, 5, modeZeroPage, opTRB}, + 0x1c: {"TRB", 3, 6, modeAbsolute, opTRB}, - 0x04: opcode{"TSB", 2, 5, modeZeroPage, opTSB}, - 0x0c: opcode{"TSB", 3, 6, modeAbsolute, opTSB}, + 0x04: {"TSB", 2, 5, modeZeroPage, opTSB}, + 0x0c: {"TSB", 3, 6, modeAbsolute, opTSB}, // Additional in Rockwell 65c02 and WDC 65c02? // They have a double addressing mode: zeropage and relative. - 0x0f: opcode{"BBR0", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(0, false)}, - 0x1f: opcode{"BBR1", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(1, false)}, - 0x2f: opcode{"BBR2", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(2, false)}, - 0x3f: opcode{"BBR3", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(3, false)}, - 0x4f: opcode{"BBR4", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(4, false)}, - 0x5f: opcode{"BBR5", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(5, false)}, - 0x6f: opcode{"BBR6", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(6, false)}, - 0x7f: opcode{"BBR7", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(7, false)}, - 0x8f: opcode{"BBS0", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(0, true)}, - 0x9f: opcode{"BBS1", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(1, true)}, - 0xaf: opcode{"BBS2", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(2, true)}, - 0xbf: opcode{"BBS3", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(3, true)}, - 0xcf: opcode{"BBS4", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(4, true)}, - 0xdf: opcode{"BBS5", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(5, true)}, - 0xef: opcode{"BBS6", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(6, true)}, - 0xff: opcode{"BBS7", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(7, true)}, + 0x0f: {"BBR0", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(0, false)}, + 0x1f: {"BBR1", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(1, false)}, + 0x2f: {"BBR2", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(2, false)}, + 0x3f: {"BBR3", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(3, false)}, + 0x4f: {"BBR4", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(4, false)}, + 0x5f: {"BBR5", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(5, false)}, + 0x6f: {"BBR6", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(6, false)}, + 0x7f: {"BBR7", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(7, false)}, + 0x8f: {"BBS0", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(0, true)}, + 0x9f: {"BBS1", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(1, true)}, + 0xaf: {"BBS2", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(2, true)}, + 0xbf: {"BBS3", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(3, true)}, + 0xcf: {"BBS4", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(4, true)}, + 0xdf: {"BBS5", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(5, true)}, + 0xef: {"BBS6", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(6, true)}, + 0xff: {"BBS7", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(7, true)}, - 0x07: opcode{"RMB0", 2, 5, modeZeroPage, buildOpSetBit(0, false)}, - 0x17: opcode{"RMB1", 2, 5, modeZeroPage, buildOpSetBit(1, false)}, - 0x27: opcode{"RMB2", 2, 5, modeZeroPage, buildOpSetBit(2, false)}, - 0x37: opcode{"RMB3", 2, 5, modeZeroPage, buildOpSetBit(3, false)}, - 0x47: opcode{"RMB4", 2, 5, modeZeroPage, buildOpSetBit(4, false)}, - 0x57: opcode{"RMB5", 2, 5, modeZeroPage, buildOpSetBit(5, false)}, - 0x67: opcode{"RMB6", 2, 5, modeZeroPage, buildOpSetBit(6, false)}, - 0x77: opcode{"RMB7", 2, 5, modeZeroPage, buildOpSetBit(7, false)}, - 0x87: opcode{"SMB0", 2, 5, modeZeroPage, buildOpSetBit(0, true)}, - 0x97: opcode{"SMB1", 2, 5, modeZeroPage, buildOpSetBit(1, true)}, - 0xa7: opcode{"SMB2", 2, 5, modeZeroPage, buildOpSetBit(2, true)}, - 0xb7: opcode{"SMB3", 2, 5, modeZeroPage, buildOpSetBit(3, true)}, - 0xc7: opcode{"SMB4", 2, 5, modeZeroPage, buildOpSetBit(4, true)}, - 0xd7: opcode{"SMB5", 2, 5, modeZeroPage, buildOpSetBit(5, true)}, - 0xe7: opcode{"SMB6", 2, 5, modeZeroPage, buildOpSetBit(6, true)}, - 0xf7: opcode{"SMB7", 2, 5, modeZeroPage, buildOpSetBit(7, true)}, + 0x07: {"RMB0", 2, 5, modeZeroPage, buildOpSetBit(0, false)}, + 0x17: {"RMB1", 2, 5, modeZeroPage, buildOpSetBit(1, false)}, + 0x27: {"RMB2", 2, 5, modeZeroPage, buildOpSetBit(2, false)}, + 0x37: {"RMB3", 2, 5, modeZeroPage, buildOpSetBit(3, false)}, + 0x47: {"RMB4", 2, 5, modeZeroPage, buildOpSetBit(4, false)}, + 0x57: {"RMB5", 2, 5, modeZeroPage, buildOpSetBit(5, false)}, + 0x67: {"RMB6", 2, 5, modeZeroPage, buildOpSetBit(6, false)}, + 0x77: {"RMB7", 2, 5, modeZeroPage, buildOpSetBit(7, false)}, + 0x87: {"SMB0", 2, 5, modeZeroPage, buildOpSetBit(0, true)}, + 0x97: {"SMB1", 2, 5, modeZeroPage, buildOpSetBit(1, true)}, + 0xa7: {"SMB2", 2, 5, modeZeroPage, buildOpSetBit(2, true)}, + 0xb7: {"SMB3", 2, 5, modeZeroPage, buildOpSetBit(3, true)}, + 0xc7: {"SMB4", 2, 5, modeZeroPage, buildOpSetBit(4, true)}, + 0xd7: {"SMB5", 2, 5, modeZeroPage, buildOpSetBit(5, true)}, + 0xe7: {"SMB6", 2, 5, modeZeroPage, buildOpSetBit(6, true)}, + 0xf7: {"SMB7", 2, 5, modeZeroPage, buildOpSetBit(7, true)}, // Maybe additional Rockwell: STP, WAI } diff --git a/core6502/nmos6502.go b/core6502/nmos6502.go index 5752591..ed1897b 100644 --- a/core6502/nmos6502.go +++ b/core6502/nmos6502.go @@ -9,181 +9,181 @@ func NewNMOS6502(m Memory) *State { } var opcodesNMOS6502 = [256]opcode{ - 0x00: opcode{"BRK", 1, 7, modeImplicit, opBRK}, - 0x4C: opcode{"JMP", 3, 3, modeAbsolute, opJMP}, - 0x6C: opcode{"JMP", 3, 3, modeIndirect, opJMP}, - 0x20: opcode{"JSR", 3, 6, modeAbsolute, opJSR}, - 0x40: opcode{"RTI", 1, 6, modeImplicit, opRTI}, - 0x60: opcode{"RTS", 1, 6, modeImplicit, opRTS}, + 0x00: {"BRK", 1, 7, modeImplicit, opBRK}, + 0x4C: {"JMP", 3, 3, modeAbsolute, opJMP}, + 0x6C: {"JMP", 3, 3, modeIndirect, opJMP}, + 0x20: {"JSR", 3, 6, modeAbsolute, opJSR}, + 0x40: {"RTI", 1, 6, modeImplicit, opRTI}, + 0x60: {"RTS", 1, 6, modeImplicit, opRTS}, - 0x48: opcode{"PHA", 1, 3, modeImplicit, buildOpPush(regA)}, - 0x08: opcode{"PHP", 1, 3, modeImplicit, buildOpPush(regP)}, - 0x68: opcode{"PLA", 1, 4, modeImplicit, buildOpPull(regA)}, - 0x28: opcode{"PLP", 1, 4, modeImplicit, buildOpPull(regP)}, + 0x48: {"PHA", 1, 3, modeImplicit, buildOpPush(regA)}, + 0x08: {"PHP", 1, 3, modeImplicit, buildOpPush(regP)}, + 0x68: {"PLA", 1, 4, modeImplicit, buildOpPull(regA)}, + 0x28: {"PLP", 1, 4, modeImplicit, buildOpPull(regP)}, - 0x09: opcode{"ORA", 2, 2, modeImmediate, buildOpLogic(operationOr)}, - 0x05: opcode{"ORA", 2, 3, modeZeroPage, buildOpLogic(operationOr)}, - 0x15: opcode{"ORA", 2, 4, modeZeroPageX, buildOpLogic(operationOr)}, - 0x0D: opcode{"ORA", 3, 4, modeAbsolute, buildOpLogic(operationOr)}, - 0x1D: opcode{"ORA", 3, 4, modeAbsoluteX, buildOpLogic(operationOr)}, // Extra cycles - 0x19: opcode{"ORA", 3, 4, modeAbsoluteY, buildOpLogic(operationOr)}, // Extra cycles - 0x01: opcode{"ORA", 2, 6, modeIndexedIndirectX, buildOpLogic(operationOr)}, - 0x11: opcode{"ORA", 2, 5, modeIndirectIndexedY, buildOpLogic(operationOr)}, // Extra cycles + 0x09: {"ORA", 2, 2, modeImmediate, buildOpLogic(operationOr)}, + 0x05: {"ORA", 2, 3, modeZeroPage, buildOpLogic(operationOr)}, + 0x15: {"ORA", 2, 4, modeZeroPageX, buildOpLogic(operationOr)}, + 0x0D: {"ORA", 3, 4, modeAbsolute, buildOpLogic(operationOr)}, + 0x1D: {"ORA", 3, 4, modeAbsoluteX, buildOpLogic(operationOr)}, // Extra cycles + 0x19: {"ORA", 3, 4, modeAbsoluteY, buildOpLogic(operationOr)}, // Extra cycles + 0x01: {"ORA", 2, 6, modeIndexedIndirectX, buildOpLogic(operationOr)}, + 0x11: {"ORA", 2, 5, modeIndirectIndexedY, buildOpLogic(operationOr)}, // Extra cycles - 0x29: opcode{"AND", 2, 2, modeImmediate, buildOpLogic(operationAnd)}, - 0x25: opcode{"AND", 2, 3, modeZeroPage, buildOpLogic(operationAnd)}, - 0x35: opcode{"AND", 2, 4, modeZeroPageX, buildOpLogic(operationAnd)}, - 0x2D: opcode{"AND", 3, 4, modeAbsolute, buildOpLogic(operationAnd)}, - 0x3D: opcode{"AND", 3, 4, modeAbsoluteX, buildOpLogic(operationAnd)}, // Extra cycles - 0x39: opcode{"AND", 3, 4, modeAbsoluteY, buildOpLogic(operationAnd)}, // Extra cycles - 0x21: opcode{"AND", 2, 6, modeIndexedIndirectX, buildOpLogic(operationAnd)}, - 0x31: opcode{"AND", 2, 5, modeIndirectIndexedY, buildOpLogic(operationAnd)}, // Extra cycles + 0x29: {"AND", 2, 2, modeImmediate, buildOpLogic(operationAnd)}, + 0x25: {"AND", 2, 3, modeZeroPage, buildOpLogic(operationAnd)}, + 0x35: {"AND", 2, 4, modeZeroPageX, buildOpLogic(operationAnd)}, + 0x2D: {"AND", 3, 4, modeAbsolute, buildOpLogic(operationAnd)}, + 0x3D: {"AND", 3, 4, modeAbsoluteX, buildOpLogic(operationAnd)}, // Extra cycles + 0x39: {"AND", 3, 4, modeAbsoluteY, buildOpLogic(operationAnd)}, // Extra cycles + 0x21: {"AND", 2, 6, modeIndexedIndirectX, buildOpLogic(operationAnd)}, + 0x31: {"AND", 2, 5, modeIndirectIndexedY, buildOpLogic(operationAnd)}, // Extra cycles - 0x49: opcode{"EOR", 2, 2, modeImmediate, buildOpLogic(operationXor)}, - 0x45: opcode{"EOR", 2, 3, modeZeroPage, buildOpLogic(operationXor)}, - 0x55: opcode{"EOR", 2, 4, modeZeroPageX, buildOpLogic(operationXor)}, - 0x4D: opcode{"EOR", 3, 4, modeAbsolute, buildOpLogic(operationXor)}, - 0x5D: opcode{"EOR", 3, 4, modeAbsoluteX, buildOpLogic(operationXor)}, // Extra cycles - 0x59: opcode{"EOR", 3, 4, modeAbsoluteY, buildOpLogic(operationXor)}, // Extra cycles - 0x41: opcode{"EOR", 2, 6, modeIndexedIndirectX, buildOpLogic(operationXor)}, - 0x51: opcode{"EOR", 2, 5, modeIndirectIndexedY, buildOpLogic(operationXor)}, // Extra cycles + 0x49: {"EOR", 2, 2, modeImmediate, buildOpLogic(operationXor)}, + 0x45: {"EOR", 2, 3, modeZeroPage, buildOpLogic(operationXor)}, + 0x55: {"EOR", 2, 4, modeZeroPageX, buildOpLogic(operationXor)}, + 0x4D: {"EOR", 3, 4, modeAbsolute, buildOpLogic(operationXor)}, + 0x5D: {"EOR", 3, 4, modeAbsoluteX, buildOpLogic(operationXor)}, // Extra cycles + 0x59: {"EOR", 3, 4, modeAbsoluteY, buildOpLogic(operationXor)}, // Extra cycles + 0x41: {"EOR", 2, 6, modeIndexedIndirectX, buildOpLogic(operationXor)}, + 0x51: {"EOR", 2, 5, modeIndirectIndexedY, buildOpLogic(operationXor)}, // Extra cycles - 0x69: opcode{"ADC", 2, 2, modeImmediate, opADC}, - 0x65: opcode{"ADC", 2, 3, modeZeroPage, opADC}, - 0x75: opcode{"ADC", 2, 4, modeZeroPageX, opADC}, - 0x6D: opcode{"ADC", 3, 4, modeAbsolute, opADC}, - 0x7D: opcode{"ADC", 3, 4, modeAbsoluteX, opADC}, // Extra cycles - 0x79: opcode{"ADC", 3, 4, modeAbsoluteY, opADC}, // Extra cycles - 0x61: opcode{"ADC", 2, 6, modeIndexedIndirectX, opADC}, - 0x71: opcode{"ADC", 2, 5, modeIndirectIndexedY, opADC}, // Extra cycles + 0x69: {"ADC", 2, 2, modeImmediate, opADC}, + 0x65: {"ADC", 2, 3, modeZeroPage, opADC}, + 0x75: {"ADC", 2, 4, modeZeroPageX, opADC}, + 0x6D: {"ADC", 3, 4, modeAbsolute, opADC}, + 0x7D: {"ADC", 3, 4, modeAbsoluteX, opADC}, // Extra cycles + 0x79: {"ADC", 3, 4, modeAbsoluteY, opADC}, // Extra cycles + 0x61: {"ADC", 2, 6, modeIndexedIndirectX, opADC}, + 0x71: {"ADC", 2, 5, modeIndirectIndexedY, opADC}, // Extra cycles - 0xE9: opcode{"SBC", 2, 2, modeImmediate, opSBC}, - 0xE5: opcode{"SBC", 2, 3, modeZeroPage, opSBC}, - 0xF5: opcode{"SBC", 2, 4, modeZeroPageX, opSBC}, - 0xED: opcode{"SBC", 3, 4, modeAbsolute, opSBC}, - 0xFD: opcode{"SBC", 3, 4, modeAbsoluteX, opSBC}, // Extra cycles - 0xF9: opcode{"SBC", 3, 4, modeAbsoluteY, opSBC}, // Extra cycles - 0xE1: opcode{"SBC", 2, 6, modeIndexedIndirectX, opSBC}, - 0xF1: opcode{"SBC", 2, 5, modeIndirectIndexedY, opSBC}, // Extra cycles + 0xE9: {"SBC", 2, 2, modeImmediate, opSBC}, + 0xE5: {"SBC", 2, 3, modeZeroPage, opSBC}, + 0xF5: {"SBC", 2, 4, modeZeroPageX, opSBC}, + 0xED: {"SBC", 3, 4, modeAbsolute, opSBC}, + 0xFD: {"SBC", 3, 4, modeAbsoluteX, opSBC}, // Extra cycles + 0xF9: {"SBC", 3, 4, modeAbsoluteY, opSBC}, // Extra cycles + 0xE1: {"SBC", 2, 6, modeIndexedIndirectX, opSBC}, + 0xF1: {"SBC", 2, 5, modeIndirectIndexedY, opSBC}, // Extra cycles - 0x24: opcode{"BIT", 2, 3, modeZeroPage, opBIT}, - 0x2C: opcode{"BIT", 3, 3, modeAbsolute, opBIT}, + 0x24: {"BIT", 2, 3, modeZeroPage, opBIT}, + 0x2C: {"BIT", 3, 3, modeAbsolute, opBIT}, - 0xC9: opcode{"CMP", 2, 2, modeImmediate, buildOpCompare(regA)}, - 0xC5: opcode{"CMP", 2, 3, modeZeroPage, buildOpCompare(regA)}, - 0xD5: opcode{"CMP", 2, 4, modeZeroPageX, buildOpCompare(regA)}, - 0xCD: opcode{"CMP", 3, 4, modeAbsolute, buildOpCompare(regA)}, - 0xDD: opcode{"CMP", 3, 4, modeAbsoluteX, buildOpCompare(regA)}, // Extra cycles - 0xD9: opcode{"CMP", 3, 4, modeAbsoluteY, buildOpCompare(regA)}, // Extra cycles - 0xC1: opcode{"CMP", 2, 6, modeIndexedIndirectX, buildOpCompare(regA)}, - 0xD1: opcode{"CMP", 2, 5, modeIndirectIndexedY, buildOpCompare(regA)}, // Extra cycles + 0xC9: {"CMP", 2, 2, modeImmediate, buildOpCompare(regA)}, + 0xC5: {"CMP", 2, 3, modeZeroPage, buildOpCompare(regA)}, + 0xD5: {"CMP", 2, 4, modeZeroPageX, buildOpCompare(regA)}, + 0xCD: {"CMP", 3, 4, modeAbsolute, buildOpCompare(regA)}, + 0xDD: {"CMP", 3, 4, modeAbsoluteX, buildOpCompare(regA)}, // Extra cycles + 0xD9: {"CMP", 3, 4, modeAbsoluteY, buildOpCompare(regA)}, // Extra cycles + 0xC1: {"CMP", 2, 6, modeIndexedIndirectX, buildOpCompare(regA)}, + 0xD1: {"CMP", 2, 5, modeIndirectIndexedY, buildOpCompare(regA)}, // Extra cycles - 0xE0: opcode{"CPX", 2, 2, modeImmediate, buildOpCompare(regX)}, - 0xE4: opcode{"CPX", 2, 3, modeZeroPage, buildOpCompare(regX)}, - 0xEC: opcode{"CPX", 3, 4, modeAbsolute, buildOpCompare(regX)}, + 0xE0: {"CPX", 2, 2, modeImmediate, buildOpCompare(regX)}, + 0xE4: {"CPX", 2, 3, modeZeroPage, buildOpCompare(regX)}, + 0xEC: {"CPX", 3, 4, modeAbsolute, buildOpCompare(regX)}, - 0xC0: opcode{"CPY", 2, 2, modeImmediate, buildOpCompare(regY)}, - 0xC4: opcode{"CPY", 2, 3, modeZeroPage, buildOpCompare(regY)}, - 0xCC: opcode{"CPY", 3, 4, modeAbsolute, buildOpCompare(regY)}, + 0xC0: {"CPY", 2, 2, modeImmediate, buildOpCompare(regY)}, + 0xC4: {"CPY", 2, 3, modeZeroPage, buildOpCompare(regY)}, + 0xCC: {"CPY", 3, 4, modeAbsolute, buildOpCompare(regY)}, - 0x2A: opcode{"ROL", 1, 2, modeAccumulator, buildOpShift(true, true)}, - 0x26: opcode{"ROL", 2, 5, modeZeroPage, buildOpShift(true, true)}, - 0x36: opcode{"ROL", 2, 6, modeZeroPageX, buildOpShift(true, true)}, - 0x2E: opcode{"ROL", 3, 6, modeAbsolute, buildOpShift(true, true)}, - 0x3E: opcode{"ROL", 3, 7, modeAbsoluteX, buildOpShift(true, true)}, + 0x2A: {"ROL", 1, 2, modeAccumulator, buildOpShift(true, true)}, + 0x26: {"ROL", 2, 5, modeZeroPage, buildOpShift(true, true)}, + 0x36: {"ROL", 2, 6, modeZeroPageX, buildOpShift(true, true)}, + 0x2E: {"ROL", 3, 6, modeAbsolute, buildOpShift(true, true)}, + 0x3E: {"ROL", 3, 7, modeAbsoluteX, buildOpShift(true, true)}, - 0x6A: opcode{"ROR", 1, 2, modeAccumulator, buildOpShift(false, true)}, - 0x66: opcode{"ROR", 2, 5, modeZeroPage, buildOpShift(false, true)}, - 0x76: opcode{"ROR", 2, 6, modeZeroPageX, buildOpShift(false, true)}, - 0x6E: opcode{"ROR", 3, 6, modeAbsolute, buildOpShift(false, true)}, - 0x7E: opcode{"ROR", 3, 7, modeAbsoluteX, buildOpShift(false, true)}, + 0x6A: {"ROR", 1, 2, modeAccumulator, buildOpShift(false, true)}, + 0x66: {"ROR", 2, 5, modeZeroPage, buildOpShift(false, true)}, + 0x76: {"ROR", 2, 6, modeZeroPageX, buildOpShift(false, true)}, + 0x6E: {"ROR", 3, 6, modeAbsolute, buildOpShift(false, true)}, + 0x7E: {"ROR", 3, 7, modeAbsoluteX, buildOpShift(false, true)}, - 0x0A: opcode{"ASL", 1, 2, modeAccumulator, buildOpShift(true, false)}, - 0x06: opcode{"ASL", 2, 5, modeZeroPage, buildOpShift(true, false)}, - 0x16: opcode{"ASL", 2, 6, modeZeroPageX, buildOpShift(true, false)}, - 0x0E: opcode{"ASL", 3, 6, modeAbsolute, buildOpShift(true, false)}, - 0x1E: opcode{"ASL", 3, 7, modeAbsoluteX, buildOpShift(true, false)}, + 0x0A: {"ASL", 1, 2, modeAccumulator, buildOpShift(true, false)}, + 0x06: {"ASL", 2, 5, modeZeroPage, buildOpShift(true, false)}, + 0x16: {"ASL", 2, 6, modeZeroPageX, buildOpShift(true, false)}, + 0x0E: {"ASL", 3, 6, modeAbsolute, buildOpShift(true, false)}, + 0x1E: {"ASL", 3, 7, modeAbsoluteX, buildOpShift(true, false)}, - 0x4A: opcode{"LSR", 1, 2, modeAccumulator, buildOpShift(false, false)}, - 0x46: opcode{"LSR", 2, 5, modeZeroPage, buildOpShift(false, false)}, - 0x56: opcode{"LSR", 2, 6, modeZeroPageX, buildOpShift(false, false)}, - 0x4E: opcode{"LSR", 3, 6, modeAbsolute, buildOpShift(false, false)}, - 0x5E: opcode{"LSR", 3, 7, modeAbsoluteX, buildOpShift(false, false)}, + 0x4A: {"LSR", 1, 2, modeAccumulator, buildOpShift(false, false)}, + 0x46: {"LSR", 2, 5, modeZeroPage, buildOpShift(false, false)}, + 0x56: {"LSR", 2, 6, modeZeroPageX, buildOpShift(false, false)}, + 0x4E: {"LSR", 3, 6, modeAbsolute, buildOpShift(false, false)}, + 0x5E: {"LSR", 3, 7, modeAbsoluteX, buildOpShift(false, false)}, - 0x38: opcode{"SEC", 1, 2, modeImplicit, buildOpUpdateFlag(flagC, true)}, - 0xF8: opcode{"SED", 1, 2, modeImplicit, buildOpUpdateFlag(flagD, true)}, - 0x78: opcode{"SEI", 1, 2, modeImplicit, buildOpUpdateFlag(flagI, true)}, - 0x18: opcode{"CLC", 1, 2, modeImplicit, buildOpUpdateFlag(flagC, false)}, - 0xD8: opcode{"CLD", 1, 2, modeImplicit, buildOpUpdateFlag(flagD, false)}, - 0x58: opcode{"CLI", 1, 2, modeImplicit, buildOpUpdateFlag(flagI, false)}, - 0xB8: opcode{"CLV", 1, 2, modeImplicit, buildOpUpdateFlag(flagV, false)}, + 0x38: {"SEC", 1, 2, modeImplicit, buildOpUpdateFlag(flagC, true)}, + 0xF8: {"SED", 1, 2, modeImplicit, buildOpUpdateFlag(flagD, true)}, + 0x78: {"SEI", 1, 2, modeImplicit, buildOpUpdateFlag(flagI, true)}, + 0x18: {"CLC", 1, 2, modeImplicit, buildOpUpdateFlag(flagC, false)}, + 0xD8: {"CLD", 1, 2, modeImplicit, buildOpUpdateFlag(flagD, false)}, + 0x58: {"CLI", 1, 2, modeImplicit, buildOpUpdateFlag(flagI, false)}, + 0xB8: {"CLV", 1, 2, modeImplicit, buildOpUpdateFlag(flagV, false)}, - 0xE6: opcode{"INC", 2, 5, modeZeroPage, buildOpIncDec(true)}, - 0xF6: opcode{"INC", 2, 6, modeZeroPageX, buildOpIncDec(true)}, - 0xEE: opcode{"INC", 3, 6, modeAbsolute, buildOpIncDec(true)}, - 0xFE: opcode{"INC", 3, 7, modeAbsoluteX, buildOpIncDec(true)}, - 0xC6: opcode{"DEC", 2, 5, modeZeroPage, buildOpIncDec(false)}, - 0xD6: opcode{"DEC", 2, 6, modeZeroPageX, buildOpIncDec(false)}, - 0xCE: opcode{"DEC", 3, 6, modeAbsolute, buildOpIncDec(false)}, - 0xDE: opcode{"DEC", 3, 7, modeAbsoluteX, buildOpIncDec(false)}, - 0xE8: opcode{"INX", 1, 2, modeImplicitX, buildOpIncDec(true)}, - 0xC8: opcode{"INY", 1, 2, modeImplicitY, buildOpIncDec(true)}, - 0xCA: opcode{"DEX", 1, 2, modeImplicitX, buildOpIncDec(false)}, - 0x88: opcode{"DEY", 1, 2, modeImplicitY, buildOpIncDec(false)}, + 0xE6: {"INC", 2, 5, modeZeroPage, buildOpIncDec(true)}, + 0xF6: {"INC", 2, 6, modeZeroPageX, buildOpIncDec(true)}, + 0xEE: {"INC", 3, 6, modeAbsolute, buildOpIncDec(true)}, + 0xFE: {"INC", 3, 7, modeAbsoluteX, buildOpIncDec(true)}, + 0xC6: {"DEC", 2, 5, modeZeroPage, buildOpIncDec(false)}, + 0xD6: {"DEC", 2, 6, modeZeroPageX, buildOpIncDec(false)}, + 0xCE: {"DEC", 3, 6, modeAbsolute, buildOpIncDec(false)}, + 0xDE: {"DEC", 3, 7, modeAbsoluteX, buildOpIncDec(false)}, + 0xE8: {"INX", 1, 2, modeImplicitX, buildOpIncDec(true)}, + 0xC8: {"INY", 1, 2, modeImplicitY, buildOpIncDec(true)}, + 0xCA: {"DEX", 1, 2, modeImplicitX, buildOpIncDec(false)}, + 0x88: {"DEY", 1, 2, modeImplicitY, buildOpIncDec(false)}, - 0xAA: opcode{"TAX", 1, 2, modeImplicit, buildOpTransfer(regA, regX)}, - 0xA8: opcode{"TAY", 1, 2, modeImplicit, buildOpTransfer(regA, regY)}, - 0x8A: opcode{"TXA", 1, 2, modeImplicit, buildOpTransfer(regX, regA)}, - 0x98: opcode{"TYA", 1, 2, modeImplicit, buildOpTransfer(regY, regA)}, - 0x9A: opcode{"TXS", 1, 2, modeImplicit, buildOpTransfer(regX, regSP)}, - 0xBA: opcode{"TSX", 1, 2, modeImplicit, buildOpTransfer(regSP, regX)}, + 0xAA: {"TAX", 1, 2, modeImplicit, buildOpTransfer(regA, regX)}, + 0xA8: {"TAY", 1, 2, modeImplicit, buildOpTransfer(regA, regY)}, + 0x8A: {"TXA", 1, 2, modeImplicit, buildOpTransfer(regX, regA)}, + 0x98: {"TYA", 1, 2, modeImplicit, buildOpTransfer(regY, regA)}, + 0x9A: {"TXS", 1, 2, modeImplicit, buildOpTransfer(regX, regSP)}, + 0xBA: {"TSX", 1, 2, modeImplicit, buildOpTransfer(regSP, regX)}, - 0xA9: opcode{"LDA", 2, 2, modeImmediate, buildOpLoad(regA)}, - 0xA5: opcode{"LDA", 2, 3, modeZeroPage, buildOpLoad(regA)}, - 0xB5: opcode{"LDA", 2, 4, modeZeroPageX, buildOpLoad(regA)}, - 0xAD: opcode{"LDA", 3, 4, modeAbsolute, buildOpLoad(regA)}, - 0xBD: opcode{"LDA", 3, 4, modeAbsoluteX, buildOpLoad(regA)}, // Extra cycles - 0xB9: opcode{"LDA", 3, 4, modeAbsoluteY, buildOpLoad(regA)}, // Extra cycles - 0xA1: opcode{"LDA", 2, 6, modeIndexedIndirectX, buildOpLoad(regA)}, - 0xB1: opcode{"LDA", 2, 5, modeIndirectIndexedY, buildOpLoad(regA)}, // Extra cycles - 0xA2: opcode{"LDX", 2, 2, modeImmediate, buildOpLoad(regX)}, - 0xA6: opcode{"LDX", 2, 3, modeZeroPage, buildOpLoad(regX)}, - 0xB6: opcode{"LDX", 2, 4, modeZeroPageY, buildOpLoad(regX)}, - 0xAE: opcode{"LDX", 3, 4, modeAbsolute, buildOpLoad(regX)}, - 0xBE: opcode{"LDX", 3, 4, modeAbsoluteY, buildOpLoad(regX)}, // Extra cycles - 0xA0: opcode{"LDY", 2, 2, modeImmediate, buildOpLoad(regY)}, - 0xA4: opcode{"LDY", 2, 3, modeZeroPage, buildOpLoad(regY)}, - 0xB4: opcode{"LDY", 2, 4, modeZeroPageX, buildOpLoad(regY)}, - 0xAC: opcode{"LDY", 3, 4, modeAbsolute, buildOpLoad(regY)}, - 0xBC: opcode{"LDY", 3, 4, modeAbsoluteX, buildOpLoad(regY)}, // Extra cycles + 0xA9: {"LDA", 2, 2, modeImmediate, buildOpLoad(regA)}, + 0xA5: {"LDA", 2, 3, modeZeroPage, buildOpLoad(regA)}, + 0xB5: {"LDA", 2, 4, modeZeroPageX, buildOpLoad(regA)}, + 0xAD: {"LDA", 3, 4, modeAbsolute, buildOpLoad(regA)}, + 0xBD: {"LDA", 3, 4, modeAbsoluteX, buildOpLoad(regA)}, // Extra cycles + 0xB9: {"LDA", 3, 4, modeAbsoluteY, buildOpLoad(regA)}, // Extra cycles + 0xA1: {"LDA", 2, 6, modeIndexedIndirectX, buildOpLoad(regA)}, + 0xB1: {"LDA", 2, 5, modeIndirectIndexedY, buildOpLoad(regA)}, // Extra cycles + 0xA2: {"LDX", 2, 2, modeImmediate, buildOpLoad(regX)}, + 0xA6: {"LDX", 2, 3, modeZeroPage, buildOpLoad(regX)}, + 0xB6: {"LDX", 2, 4, modeZeroPageY, buildOpLoad(regX)}, + 0xAE: {"LDX", 3, 4, modeAbsolute, buildOpLoad(regX)}, + 0xBE: {"LDX", 3, 4, modeAbsoluteY, buildOpLoad(regX)}, // Extra cycles + 0xA0: {"LDY", 2, 2, modeImmediate, buildOpLoad(regY)}, + 0xA4: {"LDY", 2, 3, modeZeroPage, buildOpLoad(regY)}, + 0xB4: {"LDY", 2, 4, modeZeroPageX, buildOpLoad(regY)}, + 0xAC: {"LDY", 3, 4, modeAbsolute, buildOpLoad(regY)}, + 0xBC: {"LDY", 3, 4, modeAbsoluteX, buildOpLoad(regY)}, // Extra cycles - 0x85: opcode{"STA", 2, 3, modeZeroPage, buildOpStore(regA)}, - 0x95: opcode{"STA", 2, 4, modeZeroPageX, buildOpStore(regA)}, - 0x8D: opcode{"STA", 3, 4, modeAbsolute, buildOpStore(regA)}, - 0x9D: opcode{"STA", 3, 5, modeAbsoluteX, buildOpStore(regA)}, - 0x99: opcode{"STA", 3, 5, modeAbsoluteY, buildOpStore(regA)}, - 0x81: opcode{"STA", 2, 6, modeIndexedIndirectX, buildOpStore(regA)}, - 0x91: opcode{"STA", 2, 6, modeIndirectIndexedY, buildOpStore(regA)}, - 0x86: opcode{"STX", 2, 3, modeZeroPage, buildOpStore(regX)}, - 0x96: opcode{"STX", 2, 4, modeZeroPageY, buildOpStore(regX)}, - 0x8E: opcode{"STX", 3, 4, modeAbsolute, buildOpStore(regX)}, - 0x84: opcode{"STY", 2, 3, modeZeroPage, buildOpStore(regY)}, - 0x94: opcode{"STY", 2, 4, modeZeroPageX, buildOpStore(regY)}, - 0x8C: opcode{"STY", 3, 4, modeAbsolute, buildOpStore(regY)}, + 0x85: {"STA", 2, 3, modeZeroPage, buildOpStore(regA)}, + 0x95: {"STA", 2, 4, modeZeroPageX, buildOpStore(regA)}, + 0x8D: {"STA", 3, 4, modeAbsolute, buildOpStore(regA)}, + 0x9D: {"STA", 3, 5, modeAbsoluteX, buildOpStore(regA)}, + 0x99: {"STA", 3, 5, modeAbsoluteY, buildOpStore(regA)}, + 0x81: {"STA", 2, 6, modeIndexedIndirectX, buildOpStore(regA)}, + 0x91: {"STA", 2, 6, modeIndirectIndexedY, buildOpStore(regA)}, + 0x86: {"STX", 2, 3, modeZeroPage, buildOpStore(regX)}, + 0x96: {"STX", 2, 4, modeZeroPageY, buildOpStore(regX)}, + 0x8E: {"STX", 3, 4, modeAbsolute, buildOpStore(regX)}, + 0x84: {"STY", 2, 3, modeZeroPage, buildOpStore(regY)}, + 0x94: {"STY", 2, 4, modeZeroPageX, buildOpStore(regY)}, + 0x8C: {"STY", 3, 4, modeAbsolute, buildOpStore(regY)}, - 0x90: opcode{"BCC", 2, 2, modeRelative, buildOpBranch(flagC, false)}, // Extra cycles - 0xB0: opcode{"BCS", 2, 2, modeRelative, buildOpBranch(flagC, true)}, // Extra cycles - 0xD0: opcode{"BNE", 2, 2, modeRelative, buildOpBranch(flagZ, false)}, // Extra cycles - 0xF0: opcode{"BEQ", 2, 2, modeRelative, buildOpBranch(flagZ, true)}, // Extra cycles - 0x10: opcode{"BPL", 2, 2, modeRelative, buildOpBranch(flagN, false)}, // Extra cycles - 0x30: opcode{"BMI", 2, 2, modeRelative, buildOpBranch(flagN, true)}, // Extra cycles - 0x50: opcode{"BVC", 2, 2, modeRelative, buildOpBranch(flagV, false)}, // Extra cycles - 0x70: opcode{"BVS", 2, 2, modeRelative, buildOpBranch(flagV, true)}, // Extra cycles + 0x90: {"BCC", 2, 2, modeRelative, buildOpBranch(flagC, false)}, // Extra cycles + 0xB0: {"BCS", 2, 2, modeRelative, buildOpBranch(flagC, true)}, // Extra cycles + 0xD0: {"BNE", 2, 2, modeRelative, buildOpBranch(flagZ, false)}, // Extra cycles + 0xF0: {"BEQ", 2, 2, modeRelative, buildOpBranch(flagZ, true)}, // Extra cycles + 0x10: {"BPL", 2, 2, modeRelative, buildOpBranch(flagN, false)}, // Extra cycles + 0x30: {"BMI", 2, 2, modeRelative, buildOpBranch(flagN, true)}, // Extra cycles + 0x50: {"BVC", 2, 2, modeRelative, buildOpBranch(flagV, false)}, // Extra cycles + 0x70: {"BVS", 2, 2, modeRelative, buildOpBranch(flagV, true)}, // Extra cycles - 0xEA: opcode{"NOP", 1, 2, modeImplicit, opNOP}, + 0xEA: {"NOP", 1, 2, modeImplicit, opNOP}, // Undocumented opcodes, see http://bbc.nvg.org/doc/6502OpList.txt - 0x1A: opcode{"NOP", 1, 2, modeImplicit, opNOP}, // INC A in the 65c02 - 0xC2: opcode{"NOP", 1, 2, modeImplicit, opNOP}, // Should be HALT? - 0x02: opcode{"NOP", 1, 2, modeImplicit, opNOP}, // Should be HALT? + 0x1A: {"NOP", 1, 2, modeImplicit, opNOP}, // INC A in the 65c02 + 0xC2: {"NOP", 1, 2, modeImplicit, opNOP}, // Should be HALT? + 0x02: {"NOP", 1, 2, modeImplicit, opNOP}, // Should be HALT? } diff --git a/go.sum b/go.sum index ea76f30..d3fb52c 100644 --- a/go.sum +++ b/go.sum @@ -1,6 +1,8 @@ github.com/pkg/profile v1.4.0 h1:uCmaf4vVbWAOZz36k1hrQD7ijGRzLwaME8Am/7a4jZI= github.com/pkg/profile v1.4.0/go.mod h1:NWz/XGvpEW1FyYQ7fCx4dqYBLlfTcE+A9FLAkNKqjFE= +github.com/shurcooL/httpfs v0.0.0-20190707220628-8d4bc4ba7749 h1:bUGsEnyNbVPw06Bs80sCeARAlK8lhwqGyi6UT8ymuGk= github.com/shurcooL/httpfs v0.0.0-20190707220628-8d4bc4ba7749/go.mod h1:ZY1cvUeJuFPAdZ/B6v7RHavJWZn2YPVFQ1OSXhCGOkg= +github.com/shurcooL/vfsgen v0.0.0-20181202132449-6a9ea43bcacd h1:ug7PpSOB5RBPK1Kg6qskGBoP3Vnj/aNYFTznWvlkGo0= github.com/shurcooL/vfsgen v0.0.0-20181202132449-6a9ea43bcacd/go.mod h1:TrYk7fJVaAttu97ZZKrO9UbRa8izdowaMIZcxYMbVaw= github.com/veandco/go-sdl2 v0.4.0 h1:l9q6K+Dvpd/VlZdw2ufApKnWhAQqx9UL8Zrvbjtm3Lw= github.com/veandco/go-sdl2 v0.4.0/go.mod h1:FB+kTpX9YTE+urhYiClnRzpOXbiWgaU3+5F2AB78DPg= diff --git a/izapple2sdl/sdlKeyboard.go b/izapple2sdl/sdlKeyboard.go index 4867ea6..59e0cc1 100644 --- a/izapple2sdl/sdlKeyboard.go +++ b/izapple2sdl/sdlKeyboard.go @@ -76,8 +76,9 @@ func (k *sdlKeyboard) putKey(keyEvent *sdl.KeyboardEvent) { case sdl.K_LEFT: if ctrl { result = 31 // Base64A + } else { + result = 8 } - result = 8 case sdl.K_RIGHT: result = 21 diff --git a/screen.go b/screen.go index a5effdb..9413113 100644 --- a/screen.go +++ b/screen.go @@ -58,7 +58,7 @@ func getCurrentVideoMode(a *Apple2) uint16 { isMixMode := a.io.isSoftSwitchActive(ioFlagMixed) - mode := uint16(0) + var mode uint16 if isSuperHighResMode { mode = videoSHR isMixMode = false diff --git a/traceProDOS.go b/traceProDOS.go index bccaabe..1a7c1ac 100644 --- a/traceProDOS.go +++ b/traceProDOS.go @@ -33,7 +33,7 @@ func (t *traceProDOS) inspect() { */ if t.callPending { if t.functionCode == 0x65 { - // QUIT when successfull does not return + // QUIT when successful does not return fmt.Printf("Ok \n") } else { fmt.Print("\n")