Memory manager rewritten. Logic calculated on every access.
This commit is contained in:
Ivan Izaguirre
Iván Izaguirre
parent
3618cbb9c9
commit
3660e0ae98
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@ -13,10 +13,7 @@ func newApple2plus() *Apple2 {
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a.Name = "Apple ][+"
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a.mmu = newMemoryManager(&a)
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a.cpu = core6502.NewNMOS6502(a.mmu)
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// Set the io in 0xc000
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a.io = newIoC0Page(&a)
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a.mmu.setPages(0xc0, 0xc0, a.io)
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addApple2SoftSwitches(a.io)
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return &a
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@ -28,10 +25,7 @@ func newApple2e() *Apple2 {
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a.Name = "Apple IIe"
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a.mmu = newMemoryManager(&a)
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a.cpu = core6502.NewCMOS65c02(a.mmu)
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// Set the io in 0xc000
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a.io = newIoC0Page(&a)
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a.mmu.setPages(0xc0, 0xc0, a.io)
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addApple2SoftSwitches(a.io)
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addApple2ESoftSwitches(a.io)
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@ -44,10 +38,7 @@ func newApple2eEnhanced() *Apple2 {
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a.Name = "Apple //e"
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a.mmu = newMemoryManager(&a)
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a.cpu = core6502.NewCMOS65c02(a.mmu)
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// Set the io in 0xc000
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a.io = newIoC0Page(&a)
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a.mmu.setPages(0xc0, 0xc0, a.io)
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addApple2SoftSwitches(a.io)
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addApple2ESoftSwitches(a.io)
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@ -100,8 +91,7 @@ func (a *Apple2) LoadRom(filename string) error {
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romStart = extraRomSize
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}
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mmu.physicalROM = newMemoryRange(0xd000, data[romStart:])
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mmu.resetRomPaging()
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mmu.physicalROM[0] = newMemoryRange(0xd000, data[romStart:])
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return nil
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}
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@ -15,10 +15,7 @@ func newBase64a() *Apple2 {
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a.Name = "Base 64A"
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a.mmu = newMemoryManager(&a)
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a.cpu = core6502.NewNMOS6502(a.mmu)
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// Set the io in 0xc000
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a.io = newIoC0Page(&a)
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a.mmu.setPages(0xc0, 0xc0, a.io)
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addApple2SoftSwitches(a.io)
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addBase64aSoftSwitches(a.io)
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@ -8,12 +8,6 @@ import (
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Copam BASE64A uses paginated ROM
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*/
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// Base64aROM Models the paginated ROM on a BASE64A clone
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type base64aROM struct {
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romBanks [4]*memoryRange
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romBank uint8
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}
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const (
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// There are 6 ROM chips. Each can have 4Kb or 8Kb. They can fill
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// 2 or 4 banks with 2kb windows.
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@ -43,38 +37,34 @@ func loadBase64aRom(a *Apple2) error {
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}
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// Create banks
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var r base64aROM
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for j := range romBanksBytes {
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r.romBanks[j] = newMemoryRange(0xd000, romBanksBytes[j])
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a.mmu.physicalROM[j] = newMemoryRange(0xd000, romBanksBytes[j])
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}
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// Start with first bank active
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r.changeBank(a.mmu, 0)
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a.mmu.setActiveROMPage(0)
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// Add rom soft switches. They use the annunciator 0 and 1
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a.io.addSoftSwitchRW(0x58, func(*ioC0Page) uint8 {
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r.changeBank(a.mmu, r.romBank&2)
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p := a.mmu.getActiveROMPage()
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a.mmu.setActiveROMPage(p & 2)
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return 0
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}, "ANN0OFF-ROM")
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a.io.addSoftSwitchRW(0x59, func(*ioC0Page) uint8 {
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r.changeBank(a.mmu, r.romBank|1)
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p := a.mmu.getActiveROMPage()
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a.mmu.setActiveROMPage(p | 1)
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return 0
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}, "ANN0ON-ROM")
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a.io.addSoftSwitchRW(0x5A, func(*ioC0Page) uint8 {
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r.changeBank(a.mmu, r.romBank&1)
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p := a.mmu.getActiveROMPage()
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a.mmu.setActiveROMPage(p & 1)
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return 0
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}, "ANN1OFF-ROM")
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a.io.addSoftSwitchRW(0x5B, func(*ioC0Page) uint8 {
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r.changeBank(a.mmu, r.romBank|2)
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p := a.mmu.getActiveROMPage()
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a.mmu.setActiveROMPage(p | 2)
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return 0
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}, "ANN1ON-ROM")
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return nil
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}
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func (r *base64aROM) changeBank(mmu *memoryManager, bank uint8) {
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r.romBank = bank
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//fmt.Printf("Change to ROM bank #%v\n", r.romBank)
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mmu.physicalROM = r.romBanks[r.romBank]
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mmu.resetRomPaging() // If rom was not active. This is going too far?
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}
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@ -38,12 +38,12 @@ func (c *cardBase) assign(a *Apple2, slot int) {
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c.slot = slot
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if slot != 0 && c.rom != nil {
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c.rom.base = uint16(0xc000 + slot*0x100)
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a.mmu.setPagesRead(uint8(0xc0+slot), uint8(0xc0+slot), c.rom)
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a.mmu.setCardROM(slot, c.rom)
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}
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if slot != 0 && c.romExtra != nil {
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c.romExtra.base = uint16(0xc800)
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a.mmu.prepareCardExtraRom(slot, c.romExtra)
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a.mmu.setCardROMExtra(slot, c.romExtra)
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}
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for i := 0; i < 0x10; i++ {
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@ -32,14 +32,11 @@ type cardLanguage struct {
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cardBase
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readState bool
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writeState uint8
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activeBank uint8
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ramBankA *memoryRange // First 4kb to map in 0xD000-0xDFFF
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ramBankB *memoryRange // Second 4kb to map in 0xD000-0xDFFF
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ramUpper *memoryRange // Upper 8kb to map in 0xE000-0xFFFF
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altBank bool
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}
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const (
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// Write enabling requires two sofstwitch accesses
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// Write enabling requires two softswitch accesses
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lcWriteDisabled = 0
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lcWriteHalfEnabled = 1
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lcWriteEnabled = 2
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@ -48,11 +45,9 @@ const (
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func (c *cardLanguage) assign(a *Apple2, slot int) {
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c.readState = false
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c.writeState = lcWriteEnabled
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c.activeBank = 1
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c.altBank = true
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c.ramBankA = newMemoryRange(0xd000, make([]uint8, 0x1000))
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c.ramBankB = newMemoryRange(0xd000, make([]uint8, 0x1000))
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c.ramUpper = newMemoryRange(0xe000, make([]uint8, 0x2000))
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a.mmu.initLanguageRAM(1)
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for i := uint8(0x0); i <= 0xf; i++ {
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iCopy := i
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@ -70,7 +65,7 @@ func (c *cardLanguage) assign(a *Apple2, slot int) {
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}
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func (c *cardLanguage) ssAction(ss uint8, write bool) {
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c.activeBank = (ss >> 3) & 1
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c.altBank = ((ss >> 3) & 1) == 1
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action := ss & 0x3
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switch action {
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case 0:
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@ -103,30 +98,8 @@ func (c *cardLanguage) ssAction(ss uint8, write bool) {
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c.applyState()
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}
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func (c *cardLanguage) getActiveBank() *memoryRange {
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if c.activeBank == 0 {
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return c.ramBankA
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}
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return c.ramBankB
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}
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func (c *cardLanguage) applyState() {
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mmu := c.a.mmu
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if c.readState {
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mmu.setPagesRead(0xd0, 0xdf, c.getActiveBank())
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mmu.setPagesRead(0xe0, 0xff, c.ramUpper)
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} else {
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mmu.setPagesRead(0xd0, 0xff, mmu.physicalROM)
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}
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if c.writeState == lcWriteEnabled {
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mmu.setPagesWrite(0xd0, 0xdf, c.getActiveBank())
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mmu.setPagesWrite(0xe0, 0xff, c.ramUpper)
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} else {
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mmu.setPagesWrite(0xd0, 0xff, nil)
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}
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c.a.mmu.setLanguageRAM(c.readState, c.writeState == lcWriteEnabled, c.altBank)
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}
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func (c *cardLanguage) save(w io.Writer) error {
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@ -138,23 +111,10 @@ func (c *cardLanguage) save(w io.Writer) error {
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if err != nil {
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return err
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}
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err = binary.Write(w, binary.BigEndian, c.activeBank)
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err = binary.Write(w, binary.BigEndian, c.altBank)
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if err != nil {
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return err
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}
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err = c.ramBankA.save(w)
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if err != nil {
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return err
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}
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err = c.ramBankB.save(w)
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if err != nil {
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return err
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}
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err = c.ramUpper.save(w)
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if err != nil {
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return err
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}
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return c.cardBase.save(w)
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}
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@ -167,23 +127,10 @@ func (c *cardLanguage) load(r io.Reader) error {
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if err != nil {
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return err
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}
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err = binary.Read(r, binary.BigEndian, &c.activeBank)
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err = binary.Read(r, binary.BigEndian, &c.altBank)
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if err != nil {
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return err
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}
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err = c.ramBankA.load(r)
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if err != nil {
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return err
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}
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err = c.ramBankB.load(r)
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if err != nil {
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return err
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}
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err = c.ramUpper.load(r)
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if err != nil {
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return err
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}
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c.applyState()
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return c.cardBase.load(r)
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}
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@ -24,20 +24,5 @@ func (c *cardLogger) assign(a *Apple2, slot int) {
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}, "LOGGERW")
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}
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if slot != 0 {
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a.mmu.setPagesRead(uint8(0xc0+slot), uint8(0xc0+slot), c)
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}
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c.cardBase.assign(a, slot)
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}
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// MemoryHandler implementation
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func (c *cardLogger) peek(address uint16) uint8 {
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fmt.Printf("[cardLogger] Read in %x.\n", address)
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c.a.dumpDebugInfo()
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return 0xf3
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}
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func (*cardLogger) poke(address uint16, value uint8) {
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fmt.Printf("[cardLogger] Write %x in %x.\n", value, address)
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}
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@ -17,20 +17,10 @@ type cardSaturn struct {
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cardBase
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readState bool
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writeState uint8
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activeBank uint8
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altBank bool
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activeBlock uint8
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ramBankA [saturnBlocks]*memoryRange // First 4kb to map in 0xD000-0xDFFF
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ramBankB [saturnBlocks]*memoryRange // Second 4kb to map in 0xD000-0xDFFF
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ramUpper [saturnBlocks]*memoryRange // Upper 8kb to map in 0xE000-0xFFFF
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}
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const (
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// Write enabling requires two sofstwitch accesses
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saturnWriteDisabled = 0
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saturnWriteHalfEnabled = 1
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saturnWriteEnabled = 2
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)
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const (
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saturnBlocks = 8
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)
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@ -38,13 +28,10 @@ const (
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func (c *cardSaturn) assign(a *Apple2, slot int) {
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c.readState = false
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c.writeState = lcWriteEnabled
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c.activeBank = 1
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c.altBank = true
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c.activeBlock = 0
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a.mmu.initLanguageRAM(saturnBlocks)
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for i := 0; i < saturnBlocks; i++ {
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c.ramBankA[i] = newMemoryRange(0xd000, make([]uint8, 0x1000))
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c.ramBankB[i] = newMemoryRange(0xd000, make([]uint8, 0x1000))
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c.ramUpper[i] = newMemoryRange(0xe000, make([]uint8, 0x2000))
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}
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for i := uint8(0x0); i <= 0xf; i++ {
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iCopy := i
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c.addCardSoftSwitchR(iCopy, func(*ioC0Page) uint8 {
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@ -63,22 +50,22 @@ func (c *cardSaturn) ssAction(ss uint8, write bool) {
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switch ss {
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case 0:
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// RAM read, no writes
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c.activeBank = 0
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c.altBank = false
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c.readState = true
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c.writeState = lcWriteDisabled
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case 1:
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// ROM read, RAM write
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c.activeBank = 0
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c.altBank = false
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c.readState = false
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c.writeState++
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case 2:
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// ROM read, no writes
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c.activeBank = 0
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c.altBank = false
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c.readState = false
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c.writeState = lcWriteDisabled
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case 3:
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//RAM read, RAM write
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c.activeBank = 0
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c.altBank = false
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c.readState = true
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c.writeState++
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case 4:
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@ -91,22 +78,22 @@ func (c *cardSaturn) ssAction(ss uint8, write bool) {
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c.activeBlock = 3
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case 8:
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// RAM read, no writes
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c.activeBank = 1
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c.altBank = true
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c.readState = true
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c.writeState = lcWriteDisabled
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case 9:
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// ROM read, RAM write
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c.activeBank = 1
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c.altBank = true
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c.readState = false
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c.writeState++
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case 10:
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// ROM read, no writes
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c.activeBank = 1
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c.altBank = true
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c.readState = false
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c.writeState = lcWriteDisabled
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case 11:
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//RAM read, RAM write
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c.activeBank = 1
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c.altBank = true
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c.readState = true
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c.writeState++
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case 12:
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@ -131,30 +118,9 @@ func (c *cardSaturn) ssAction(ss uint8, write bool) {
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c.applyState()
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}
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func (c *cardSaturn) getActiveBank() [8]*memoryRange {
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if c.activeBank == 0 {
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return c.ramBankA
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}
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return c.ramBankB
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}
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func (c *cardSaturn) applyState() {
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mmu := c.a.mmu
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block := c.activeBlock
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if c.readState {
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mmu.setPagesRead(0xd0, 0xdf, c.getActiveBank()[block])
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mmu.setPagesRead(0xe0, 0xff, c.ramUpper[block])
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} else {
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mmu.setPagesRead(0xd0, 0xff, mmu.physicalROM)
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}
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if c.writeState == lcWriteEnabled {
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mmu.setPagesWrite(0xd0, 0xdf, c.getActiveBank()[block])
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mmu.setPagesWrite(0xe0, 0xff, c.ramUpper[block])
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} else {
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mmu.setPagesWrite(0xd0, 0xff, nil)
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}
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c.a.mmu.setLanguageRAMBlock(c.activeBlock)
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c.a.mmu.setLanguageRAM(c.readState, c.writeState == lcWriteEnabled, c.altBank)
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}
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func (c *cardSaturn) save(w io.Writer) error {
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@ -167,7 +133,7 @@ func (c *cardSaturn) save(w io.Writer) error {
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if err != nil {
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return err
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}
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err = binary.Write(w, binary.BigEndian, c.activeBank)
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err = binary.Write(w, binary.BigEndian, c.altBank)
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if err != nil {
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return err
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}
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@ -175,18 +141,6 @@ func (c *cardSaturn) save(w io.Writer) error {
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if err != nil {
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return err
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}
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err = c.ramBankA[i].save(w)
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if err != nil {
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return err
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}
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err = c.ramBankB[i].save(w)
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if err != nil {
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return err
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}
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err = c.ramUpper[i].save(w)
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if err != nil {
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return err
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}
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}
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return c.cardBase.save(w)
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}
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@ -201,7 +155,7 @@ func (c *cardSaturn) load(r io.Reader) error {
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if err != nil {
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return err
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}
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err = binary.Read(r, binary.BigEndian, &c.activeBank)
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err = binary.Read(r, binary.BigEndian, &c.altBank)
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if err != nil {
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return err
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}
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@ -209,16 +163,6 @@ func (c *cardSaturn) load(r io.Reader) error {
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if err != nil {
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return err
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}
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err = c.ramBankA[i].load(r)
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if err != nil {
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return err
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}
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err = c.ramBankB[i].load(r)
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if err != nil {
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return err
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}
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err = c.ramUpper[i].load(r)
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c.applyState()
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}
|
||||
return c.cardBase.load(r)
|
||||
|
|
|
|||
|
|
@ -114,6 +114,9 @@ func (p *ioC0Page) peek(address uint16) uint8 {
|
|||
pageAddress := uint8(address)
|
||||
ss := p.softSwitchesR[pageAddress]
|
||||
if ss == nil {
|
||||
if p.trace {
|
||||
fmt.Printf("Unknown softswitch on read to $%04x\n", address)
|
||||
}
|
||||
if p.panicNotImplemented {
|
||||
panic(fmt.Sprintf("Unknown softswitch on read to $%04x", address))
|
||||
}
|
||||
|
|
@ -131,6 +134,9 @@ func (p *ioC0Page) poke(address uint16, value uint8) {
|
|||
pageAddress := uint8(address)
|
||||
ss := p.softSwitchesW[pageAddress]
|
||||
if ss == nil {
|
||||
if p.trace {
|
||||
fmt.Printf("Unknown softswitch on write to $%04x\n", address)
|
||||
}
|
||||
if p.panicNotImplemented {
|
||||
panic(fmt.Sprintf("Unknown softswitch on write to $%04x", address))
|
||||
}
|
||||
|
|
|
|||
309
memoryManager.go
309
memoryManager.go
|
|
@ -2,6 +2,7 @@ package apple2
|
|||
|
||||
import (
|
||||
"encoding/binary"
|
||||
"fmt"
|
||||
"io"
|
||||
)
|
||||
|
||||
|
|
@ -10,137 +11,218 @@ import (
|
|||
|
||||
type memoryManager struct {
|
||||
apple2 *Apple2
|
||||
// Map of assigned pages
|
||||
activeMemoryRead [256]memoryHandler
|
||||
activeMemoryWrite [256]memoryHandler
|
||||
|
||||
// Pages prepared to be paged in and out
|
||||
physicalMainRAM *memoryRange // 0x0000 to 0xbfff, Up to 48 Kb
|
||||
physicalROM memoryHandler // 0xd000 to 0xffff, 12 Kb
|
||||
physicalROMe memoryHandler // 0xc000 to 0xcfff, Zero or 4bk in the Apple2e
|
||||
// Main RAM area: 0x0000 to 0xbfff
|
||||
physicalMainRAM *memoryRange // 0x0000 to 0xbfff, Up to 48 Kb
|
||||
physicalMainRAMAlt *memoryRange // 0x0000 to 0xbfff, Up to 48 Kb. Additional
|
||||
|
||||
// Pages prapared for optional card ROM banks
|
||||
activeSlot uint8
|
||||
cardsROMExtra [8]memoryHandler // 0xc800 to 0xcfff. for each card
|
||||
// Slots area: 0xc000 to 0xcfff
|
||||
cardsROM [8]memoryHandler //0xcs00 to 0xcsff. 256 bytes for each card
|
||||
cardsROMExtra [8]memoryHandler // 0xc800 to 0xcfff. 2048 bytes for each card
|
||||
physicalROMe memoryHandler // 0xc100 to 0xcfff, Zero or 4kb in the Apple2e
|
||||
|
||||
// Upper area: 0xd000 to 0xffff
|
||||
physicalROM [4]memoryHandler // 0xd000 to 0xffff, 12 Kb. Up to four banks
|
||||
physicalDRAM []memoryHandler // 0xd000 to 0xdfff, 4KB. Up to 8 banks.
|
||||
physicalDAltRAM []memoryHandler // 0xd000 to 0xdfff, 4KB. Up to 8 banks.
|
||||
physicalEFRAM []memoryHandler // 0xe000 to 0xffff, 8KB. Up to 8 banks.
|
||||
|
||||
// Pages prapared for optional card ROM banks in 0xc800 to 0xcfff
|
||||
altMainRAMActiveRead bool // Use extra RAM on the 128KB Apple2e for read
|
||||
altMainRAMActiveWrite bool // Use extra RAM on the 128KB Apple2e for write
|
||||
|
||||
c3ROMActive bool // Apple2e slot 3 ROM shadow
|
||||
cxROMActive bool // Apple2e slots ROM shadow
|
||||
activeSlot uint8 // Active slot owner of 0xc800 to 0xcfff
|
||||
|
||||
lcSelectedBlock uint8 // Language card block selected. Usually, allways 0. But Saturn has 8
|
||||
lcActiveRead bool // Upper RAM active for read
|
||||
lcActiveWrite bool // Upper RAM active for read
|
||||
lcAltBank bool // Alternate
|
||||
romPage uint8 // Active ROM page
|
||||
}
|
||||
|
||||
const (
|
||||
ioC8Off uint16 = 0xcfff
|
||||
addressLimitMainRAM uint16 = 0xbfff
|
||||
addressLimitIO uint16 = 0xc0ff
|
||||
addressLimitSlots uint16 = 0xc7ff
|
||||
addressLimitSlotsExtra uint16 = 0xcfff
|
||||
addressLimitDArea uint16 = 0xdfff
|
||||
)
|
||||
|
||||
type memoryHandler interface {
|
||||
peek(uint16) uint8
|
||||
poke(uint16, uint8)
|
||||
}
|
||||
|
||||
const (
|
||||
ioC8Off uint16 = 0xCFFF
|
||||
)
|
||||
|
||||
func (mmu *memoryManager) access(address uint16, activeMemory *[256]memoryHandler) memoryHandler {
|
||||
if address == ioC8Off {
|
||||
mmu.resetSlotExpansionRoms()
|
||||
}
|
||||
|
||||
hi := uint8(address >> 8)
|
||||
if hi >= 0xC1 && hi <= 0xC7 {
|
||||
slot := hi - 0xC0
|
||||
if slot != mmu.activeSlot {
|
||||
mmu.activateCardRomExtra(slot)
|
||||
}
|
||||
}
|
||||
mh := activeMemory[hi]
|
||||
if mh == nil {
|
||||
return nil
|
||||
}
|
||||
return mh
|
||||
}
|
||||
|
||||
// Peek returns the data on the given address
|
||||
func (mmu *memoryManager) Peek(address uint16) uint8 {
|
||||
mh := mmu.access(address, &mmu.activeMemoryRead)
|
||||
if mh == nil {
|
||||
return 0xf4 // Or some random number
|
||||
}
|
||||
return mh.peek(address)
|
||||
}
|
||||
|
||||
// Poke sets the data at the given address
|
||||
func (mmu *memoryManager) Poke(address uint16, value uint8) {
|
||||
mh := mmu.access(address, &mmu.activeMemoryWrite)
|
||||
if mh == nil {
|
||||
return
|
||||
}
|
||||
mh.poke(address, value)
|
||||
}
|
||||
|
||||
func (mmu *memoryManager) setPages(begin uint8, end uint8, mh memoryHandler) {
|
||||
mmu.setPagesRead(begin, end, mh)
|
||||
mmu.setPagesWrite(begin, end, mh)
|
||||
}
|
||||
|
||||
func (mmu *memoryManager) setPagesRead(begin uint8, end uint8, mh memoryHandler) {
|
||||
i := begin
|
||||
for {
|
||||
mmu.activeMemoryRead[i] = mh
|
||||
if i == end {
|
||||
break
|
||||
}
|
||||
i++
|
||||
}
|
||||
}
|
||||
|
||||
func (mmu *memoryManager) setPagesWrite(begin uint8, end uint8, mh memoryHandler) {
|
||||
i := begin
|
||||
for {
|
||||
mmu.activeMemoryWrite[i] = mh
|
||||
if i == end {
|
||||
break
|
||||
}
|
||||
i++
|
||||
}
|
||||
}
|
||||
|
||||
func (mmu *memoryManager) prepareCardExtraRom(slot int, mh memoryHandler) {
|
||||
mmu.cardsROMExtra[slot] = mh
|
||||
}
|
||||
|
||||
// When 0xcfff is accessed the card expansion rom is unassigned
|
||||
func (mmu *memoryManager) resetSlotExpansionRoms() {
|
||||
if mmu.apple2.io.isSoftSwitchActive(ioFlagIntCxRom) {
|
||||
// Ignore if the Apple2 shadow ROM is active
|
||||
return
|
||||
}
|
||||
mmu.activeSlot = 0
|
||||
mmu.setPagesRead(0xc8, 0xcf, nil)
|
||||
}
|
||||
|
||||
// When a card base ROM is accesed the extra rom is assigned if available
|
||||
func (mmu *memoryManager) activateCardRomExtra(slot uint8) {
|
||||
//fmt.Printf("Activate slot %v\n", slot)
|
||||
if mmu.cardsROMExtra[slot] != nil {
|
||||
mmu.setPagesRead(0xC8, 0xCF, mmu.cardsROMExtra[slot])
|
||||
}
|
||||
mmu.activeSlot = slot
|
||||
}
|
||||
|
||||
func (mmu *memoryManager) resetRomPaging() {
|
||||
// Assign the first 12kb of ROM from 0xd000 to 0xffff
|
||||
mmu.setPagesRead(0xd0, 0xff, mmu.physicalROM)
|
||||
}
|
||||
|
||||
func (mmu *memoryManager) resetBaseRamPaging() {
|
||||
// Assign the base RAM from 0x0000 to 0xbfff
|
||||
mmu.setPages(0x00, 0xbf, mmu.physicalMainRAM)
|
||||
}
|
||||
|
||||
func newMemoryManager(a *Apple2) *memoryManager {
|
||||
var mmu memoryManager
|
||||
mmu.apple2 = a
|
||||
|
||||
ram := make([]uint8, 0xc000) // Reserve 48kb
|
||||
mmu.physicalMainRAM = newMemoryRange(0, ram)
|
||||
mmu.resetBaseRamPaging()
|
||||
|
||||
return &mmu
|
||||
}
|
||||
|
||||
func (mmu *memoryManager) accessRead(address uint16) memoryHandler {
|
||||
// Main RAM area
|
||||
if address <= addressLimitMainRAM {
|
||||
if mmu.altMainRAMActiveRead {
|
||||
return mmu.physicalMainRAMAlt
|
||||
}
|
||||
return mmu.physicalMainRAM
|
||||
}
|
||||
|
||||
// IO section
|
||||
if address <= addressLimitIO {
|
||||
return mmu.apple2.io
|
||||
}
|
||||
|
||||
// Slots sections
|
||||
if address <= addressLimitSlotsExtra {
|
||||
slot := uint8((address >> 8) & 0x07)
|
||||
if mmu.cxROMActive {
|
||||
return mmu.physicalROMe
|
||||
}
|
||||
// First slot area
|
||||
if address <= addressLimitSlots {
|
||||
if mmu.c3ROMActive && (slot == 3) {
|
||||
return mmu.physicalROMe
|
||||
}
|
||||
mmu.activeSlot = slot
|
||||
return mmu.cardsROM[slot]
|
||||
}
|
||||
// Extra slot area
|
||||
if address == ioC8Off {
|
||||
// Reset extra slot area owner
|
||||
mmu.activeSlot = 0
|
||||
}
|
||||
return mmu.cardsROMExtra[slot]
|
||||
}
|
||||
|
||||
// Upper address area
|
||||
if mmu.lcActiveRead {
|
||||
if address <= addressLimitDArea {
|
||||
if mmu.lcAltBank {
|
||||
return mmu.physicalDAltRAM[mmu.lcSelectedBlock]
|
||||
}
|
||||
return mmu.physicalDRAM[mmu.lcSelectedBlock]
|
||||
}
|
||||
return mmu.physicalEFRAM[mmu.lcSelectedBlock]
|
||||
}
|
||||
|
||||
// Use ROM
|
||||
return mmu.physicalROM[mmu.romPage]
|
||||
}
|
||||
|
||||
func (mmu *memoryManager) accessWrite(address uint16) memoryHandler {
|
||||
// Main RAM area
|
||||
if address <= addressLimitMainRAM {
|
||||
if mmu.altMainRAMActiveWrite {
|
||||
return mmu.physicalMainRAMAlt
|
||||
}
|
||||
return mmu.physicalMainRAM
|
||||
}
|
||||
|
||||
// IO section
|
||||
if address <= addressLimitIO {
|
||||
return mmu.apple2.io
|
||||
}
|
||||
|
||||
// Slots sections
|
||||
if address <= addressLimitSlotsExtra {
|
||||
slot := uint8((address >> 8) & 0x07)
|
||||
// First slot area
|
||||
if address <= addressLimitSlots {
|
||||
mmu.activeSlot = slot
|
||||
return mmu.cardsROM[slot]
|
||||
}
|
||||
// Extra slot area
|
||||
if address == ioC8Off {
|
||||
// Reset extra slot area owner
|
||||
mmu.activeSlot = 0
|
||||
}
|
||||
return mmu.cardsROMExtra[slot]
|
||||
}
|
||||
|
||||
// Upper address area
|
||||
if mmu.lcActiveWrite {
|
||||
if address <= addressLimitDArea {
|
||||
if mmu.lcAltBank {
|
||||
return mmu.physicalDAltRAM[mmu.lcSelectedBlock]
|
||||
}
|
||||
return mmu.physicalDRAM[mmu.lcSelectedBlock]
|
||||
}
|
||||
return mmu.physicalEFRAM[mmu.lcSelectedBlock]
|
||||
}
|
||||
|
||||
// Use ROM
|
||||
return mmu.physicalROM[mmu.romPage]
|
||||
}
|
||||
|
||||
// Peek returns the data on the given address
|
||||
func (mmu *memoryManager) Peek(address uint16) uint8 {
|
||||
mh := mmu.accessRead(address)
|
||||
if mh == nil {
|
||||
fmt.Printf("Reading void addressing 0x%x\n", address)
|
||||
return 0xf4 // Or some random number
|
||||
}
|
||||
return mh.peek(address)
|
||||
}
|
||||
|
||||
// Poke sets the data at the given address
|
||||
func (mmu *memoryManager) Poke(address uint16, value uint8) {
|
||||
mh := mmu.accessWrite(address)
|
||||
if mh == nil {
|
||||
fmt.Printf("Writing to void addressing 0x%x\n", address)
|
||||
return
|
||||
}
|
||||
mh.poke(address, value)
|
||||
}
|
||||
|
||||
// Memory initialization
|
||||
func (mmu *memoryManager) setCardROM(slot int, mh memoryHandler) {
|
||||
mmu.cardsROM[slot] = mh
|
||||
}
|
||||
|
||||
func (mmu *memoryManager) setCardROMExtra(slot int, mh memoryHandler) {
|
||||
mmu.cardsROMExtra[slot] = mh
|
||||
}
|
||||
|
||||
func (mmu *memoryManager) initLanguageRAM(groups int) {
|
||||
mmu.physicalDRAM = make([]memoryHandler, groups)
|
||||
mmu.physicalDAltRAM = make([]memoryHandler, groups)
|
||||
mmu.physicalEFRAM = make([]memoryHandler, groups)
|
||||
for i := 0; i < groups; i++ {
|
||||
mmu.physicalDRAM[i] = newMemoryRange(0xd000, make([]uint8, 0x1000))
|
||||
mmu.physicalDAltRAM[i] = newMemoryRange(0xd000, make([]uint8, 0x1000))
|
||||
mmu.physicalEFRAM[i] = newMemoryRange(0xe000, make([]uint8, 0x2000))
|
||||
}
|
||||
}
|
||||
|
||||
// Memory configuration
|
||||
func (mmu *memoryManager) setActiveROMPage(page uint8) {
|
||||
mmu.romPage = page
|
||||
}
|
||||
|
||||
func (mmu *memoryManager) getActiveROMPage() uint8 {
|
||||
return mmu.romPage
|
||||
}
|
||||
|
||||
func (mmu *memoryManager) setLanguageRAM(readActive bool, writeActive bool, altBank bool) {
|
||||
mmu.lcActiveRead = readActive
|
||||
mmu.lcActiveWrite = writeActive
|
||||
mmu.lcAltBank = altBank
|
||||
}
|
||||
|
||||
func (mmu *memoryManager) setLanguageRAMBlock(block uint8) {
|
||||
block = block % uint8(len(mmu.physicalDRAM))
|
||||
mmu.lcSelectedBlock = block
|
||||
}
|
||||
|
||||
// TODO: complete save and load
|
||||
func (mmu *memoryManager) save(w io.Writer) error {
|
||||
err := mmu.physicalMainRAM.save(w)
|
||||
if err != nil {
|
||||
|
|
@ -162,8 +244,7 @@ func (mmu *memoryManager) load(r io.Reader) error {
|
|||
if err != nil {
|
||||
return err
|
||||
}
|
||||
mmu.activateCardRomExtra(mmu.activeSlot)
|
||||
// mmu.activateCardRomExtra(mmu.activeSlot)
|
||||
|
||||
mmu.resetBaseRamPaging()
|
||||
return nil
|
||||
}
|
||||
|
|
|
|||
|
|
@ -82,21 +82,21 @@ func getSoftSwitchExt(ioFlag uint8, dstValue uint8, action softSwitchExtAction)
|
|||
}
|
||||
|
||||
func softSwitchIntCxRomOn(io *ioC0Page) {
|
||||
io.apple2.mmu.setPagesRead(0xc1, 0xcf, io.apple2.mmu.physicalROMe)
|
||||
//io.apple2.mmu.setPagesRead(0xc1, 0xcf, io.apple2.mmu.physicalROMe)
|
||||
}
|
||||
|
||||
func softSwitchIntCxRomOff(io *ioC0Page) {
|
||||
// TODO restore all the ROM from the slots for 0xc1 to 0xc7
|
||||
io.apple2.mmu.setPages(0xc1, 0xc7, nil)
|
||||
//io.apple2.mmu.setPages(0xc1, 0xc7, nil)
|
||||
}
|
||||
|
||||
func softSwitchSlotC3RomOn(io *ioC0Page) {
|
||||
// TODO restore the slot 3 ROM
|
||||
io.apple2.mmu.setPages(0xc3, 0xc3, nil)
|
||||
//io.apple2.mmu.setPages(0xc3, 0xc3, nil)
|
||||
}
|
||||
|
||||
func softSwitchSlotC3RomOff(io *ioC0Page) {
|
||||
io.apple2.mmu.setPagesRead(0xc3, 0xc3, io.apple2.mmu.physicalROMe)
|
||||
//io.apple2.mmu.setPagesRead(0xc3, 0xc3, io.apple2.mmu.physicalROMe)
|
||||
}
|
||||
|
||||
// TODO: apply state after persistance load
|
||||
|
|
|
|||
Loading…
Reference in New Issue