Fixed JSR and BRK. Added disassemble.
This commit is contained in:
Ivan Izaguirre
parent
ff0d3d10c9
commit
6e524093c1
160
execute.go
160
execute.go
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@ -11,20 +11,23 @@ func step(s *state) {
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}
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const modeNone = -1
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const modeImmediate = 0
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const modeZeroPage = 1
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const modeZeroPageX = 3
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const modeZeroPageY = 6
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const modeAbsolute = 2
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const modeAbsoluteX = 4
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const modeAbsoluteY = 5
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const modeIndexedIndirectX = 7
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const modeIndirectIndexedY = 8
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const modeAccumulator = 9
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const modeRegisterX = 10
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const modeRegisterY = 11
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const modeIndirect = 12
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const (
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modeImplicit = iota + 1
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modeImplicitX
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modeImplicitY
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modeAccumulator
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modeImmediate
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modeZeroPage
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modeZeroPageX
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modeZeroPageY
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modeRelative
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modeAbsolute
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modeAbsoluteX
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modeAbsoluteY
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modeIndirect
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modeIndexedIndirectX
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modeIndirectIndexedY
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)
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// https://www.masswerk.at/6502/6502_instruction_set.html
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// http://www.emulator101.com/reference/6502-reference.html
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@ -44,11 +47,11 @@ func resolve(s *state, line []uint8, opcode opcode) (value uint8, address uint16
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value = s.registers.getA()
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hasAddress = false
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register = regA
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case modeRegisterX:
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case modeImplicitX:
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value = s.registers.getX()
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hasAddress = false
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register = regX
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case modeRegisterY:
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case modeImplicitY:
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value = s.registers.getY()
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hasAddress = false
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register = regY
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@ -219,7 +222,7 @@ func opADC(s *state, line []uint8, opcode opcode) {
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value, _, _ := resolve(s, line, opcode)
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if s.registers.getFlag(flagD) {
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// TODO BCD. See http://www.6502.org/tutorials/decimal_mode.html
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panic("BCD not supported")
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} else {
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total := uint16(s.registers.getA()) +
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uint16(value) +
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@ -236,6 +239,7 @@ func opSBC(s *state, line []uint8, opcode opcode) {
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value, _, _ := resolve(s, line, opcode)
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if s.registers.getFlag(flagD) {
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// TODO BCD
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panic("BCD not supported")
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} else {
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total := 0x100 + uint16(s.registers.getA()) -
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uint16(value) -
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@ -300,8 +304,9 @@ func opJMP(s *state, line []uint8, opcode opcode) {
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func opNOP(s *state, line []uint8, opcode opcode) {}
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func opJSR(s *state, line []uint8, opcode opcode) {
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pushWord(s, s.registers.getPC())
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s.registers.setPC(getWordInLine(line))
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pushWord(s, s.registers.getPC()-1)
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_, address, _ := resolve(s, line, opcode)
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s.registers.setPC(address)
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}
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func opRTI(s *state, line []uint8, opcode opcode) {
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@ -310,28 +315,28 @@ func opRTI(s *state, line []uint8, opcode opcode) {
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}
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func opRTS(s *state, line []uint8, opcode opcode) {
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s.registers.setPC(pullWord(s) + 1) // TODO: Do we really need to add 1?
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s.registers.setPC(pullWord(s) + 1)
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}
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func opBRK(s *state, line []uint8, opcode opcode) {
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s.registers.setFlag(flagI)
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pushWord(s, s.registers.getPC()+1) // TODO: De we have to add 1 or 2?
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pushWord(s, s.registers.getPC()+1)
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pushByte(s, s.registers.getP()|(flagB+flag5))
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s.registers.setFlag(flagI)
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s.registers.setPC(s.memory.getWord(0xFFFE))
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}
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var opcodes = [256]opcode{
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0x00: opcode{"BRK", 1, 7, modeNone, opBRK},
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0x00: opcode{"BRK", 1, 7, modeImplicit, opBRK},
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0x4C: opcode{"JMP", 3, 3, modeAbsolute, opJMP},
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0x6C: opcode{"JMP", 3, 3, modeIndirect, opJMP},
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0x20: opcode{"JSR", 3, 6, modeNone, opJSR},
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0x40: opcode{"RTI", 1, 6, modeNone, opRTI},
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0x60: opcode{"RTS", 1, 6, modeNone, opRTS},
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0x20: opcode{"JSR", 3, 6, modeAbsolute, opJSR},
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0x40: opcode{"RTI", 1, 6, modeImplicit, opRTI},
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0x60: opcode{"RTS", 1, 6, modeImplicit, opRTS},
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0x48: opcode{"PHA", 1, 3, modeNone, opPHA},
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0x08: opcode{"PHP", 1, 3, modeNone, opPHP},
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0x68: opcode{"PLA", 1, 4, modeNone, opPLA},
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0x28: opcode{"PLP", 1, 4, modeNone, opPLP},
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0x48: opcode{"PHA", 1, 3, modeImplicit, opPHA},
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0x08: opcode{"PHP", 1, 3, modeImplicit, opPHP},
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0x68: opcode{"PLA", 1, 4, modeImplicit, opPLA},
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0x28: opcode{"PLP", 1, 4, modeImplicit, opPLP},
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0x09: opcode{"ORA", 2, 2, modeImmediate, buildOpLogic(operationOr)},
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0x05: opcode{"ORA", 2, 3, modeZeroPage, buildOpLogic(operationOr)},
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@ -379,7 +384,7 @@ var opcodes = [256]opcode{
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0xF1: opcode{"SBC", 2, 5, modeIndirectIndexedY, opSBC}, // Extra cycles
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0x24: opcode{"BIT", 2, 3, modeZeroPage, opBIT},
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0x2C: opcode{"BIT", 2, 3, modeAbsolute, opBIT},
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0x2C: opcode{"BIT", 3, 3, modeAbsolute, opBIT},
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0xC9: opcode{"CMP", 2, 2, modeImmediate, buildOpCompare(regA)},
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0xC5: opcode{"CMP", 2, 3, modeZeroPage, buildOpCompare(regA)},
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@ -422,13 +427,13 @@ var opcodes = [256]opcode{
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0x4E: opcode{"LSR", 3, 6, modeAbsolute, buildOpShift(false, false)},
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0x5E: opcode{"LSR", 3, 7, modeAbsoluteX, buildOpShift(false, false)},
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0x38: opcode{"SEC", 1, 2, modeNone, buildOpUpdateFlag(flagC, true)},
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0xF8: opcode{"SED", 1, 2, modeNone, buildOpUpdateFlag(flagD, true)},
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0x78: opcode{"SEI", 1, 2, modeNone, buildOpUpdateFlag(flagI, true)},
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0x18: opcode{"CLC", 1, 2, modeNone, buildOpUpdateFlag(flagC, false)},
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0xD8: opcode{"CLD", 1, 2, modeNone, buildOpUpdateFlag(flagD, false)},
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0x58: opcode{"CLI", 1, 2, modeNone, buildOpUpdateFlag(flagI, false)},
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0xB8: opcode{"CLV", 1, 2, modeNone, buildOpUpdateFlag(flagV, false)},
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0x38: opcode{"SEC", 1, 2, modeImplicit, buildOpUpdateFlag(flagC, true)},
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0xF8: opcode{"SED", 1, 2, modeImplicit, buildOpUpdateFlag(flagD, true)},
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0x78: opcode{"SEI", 1, 2, modeImplicit, buildOpUpdateFlag(flagI, true)},
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0x18: opcode{"CLC", 1, 2, modeImplicit, buildOpUpdateFlag(flagC, false)},
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0xD8: opcode{"CLD", 1, 2, modeImplicit, buildOpUpdateFlag(flagD, false)},
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0x58: opcode{"CLI", 1, 2, modeImplicit, buildOpUpdateFlag(flagI, false)},
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0xB8: opcode{"CLV", 1, 2, modeImplicit, buildOpUpdateFlag(flagV, false)},
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0xE6: opcode{"INC", 2, 5, modeZeroPage, buildOpIncDec(true)},
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0xF6: opcode{"INC", 2, 6, modeZeroPageX, buildOpIncDec(true)},
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@ -438,17 +443,17 @@ var opcodes = [256]opcode{
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0xD6: opcode{"DEC", 2, 6, modeZeroPageX, buildOpIncDec(false)},
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0xCE: opcode{"DEC", 3, 6, modeAbsolute, buildOpIncDec(false)},
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0xDE: opcode{"DEC", 3, 7, modeAbsoluteX, buildOpIncDec(false)},
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0xE8: opcode{"INX", 1, 2, modeRegisterX, buildOpIncDec(true)},
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0xC8: opcode{"INY", 1, 2, modeRegisterY, buildOpIncDec(true)},
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0xCA: opcode{"DEX", 1, 2, modeRegisterX, buildOpIncDec(false)},
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0x88: opcode{"DEY", 1, 2, modeRegisterY, buildOpIncDec(false)},
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0xE8: opcode{"INX", 1, 2, modeImplicitX, buildOpIncDec(true)},
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0xC8: opcode{"INY", 1, 2, modeImplicitY, buildOpIncDec(true)},
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0xCA: opcode{"DEX", 1, 2, modeImplicitX, buildOpIncDec(false)},
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0x88: opcode{"DEY", 1, 2, modeImplicitY, buildOpIncDec(false)},
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0xAA: opcode{"TAX", 1, 2, modeNone, buildOpTransfer(regA, regX)},
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0xA8: opcode{"TAY", 1, 2, modeNone, buildOpTransfer(regA, regY)},
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0x8A: opcode{"TXA", 1, 2, modeNone, buildOpTransfer(regX, regA)},
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0x98: opcode{"TYA", 1, 2, modeNone, buildOpTransfer(regY, regA)},
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0x9A: opcode{"TXS", 1, 2, modeNone, buildOpTransfer(regX, regSP)},
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0xBA: opcode{"TSX", 1, 2, modeNone, buildOpTransfer(regSP, regX)},
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0xAA: opcode{"TAX", 1, 2, modeImplicit, buildOpTransfer(regA, regX)},
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0xA8: opcode{"TAY", 1, 2, modeImplicit, buildOpTransfer(regA, regY)},
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0x8A: opcode{"TXA", 1, 2, modeImplicit, buildOpTransfer(regX, regA)},
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0x98: opcode{"TYA", 1, 2, modeImplicit, buildOpTransfer(regY, regA)},
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0x9A: opcode{"TXS", 1, 2, modeImplicit, buildOpTransfer(regX, regSP)},
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0xBA: opcode{"TSX", 1, 2, modeImplicit, buildOpTransfer(regSP, regX)},
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0xA9: opcode{"LDA", 2, 2, modeImmediate, buildOpLoad(regA)},
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0xA5: opcode{"LDA", 2, 3, modeZeroPage, buildOpLoad(regA)},
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@ -483,16 +488,16 @@ var opcodes = [256]opcode{
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0x94: opcode{"STY", 2, 4, modeZeroPageX, buildOpStore(regY)},
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0x8C: opcode{"STY", 3, 4, modeAbsolute, buildOpStore(regY)},
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0x90: opcode{"BCC", 2, 2, modeNone, buildOpBranch(flagC, false)}, // Extra cycles
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0xB0: opcode{"BCS", 2, 2, modeNone, buildOpBranch(flagC, true)}, // Extra cycles
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0xD0: opcode{"BNE", 2, 2, modeNone, buildOpBranch(flagZ, false)}, // Extra cycles
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0xF0: opcode{"BEQ", 2, 2, modeNone, buildOpBranch(flagZ, true)}, // Extra cycles
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0x10: opcode{"BPL", 2, 2, modeNone, buildOpBranch(flagN, false)}, // Extra cycles
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0x30: opcode{"BMI", 2, 2, modeNone, buildOpBranch(flagN, true)}, // Extra cycles
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0x50: opcode{"BVC", 2, 2, modeNone, buildOpBranch(flagV, false)}, // Extra cycles
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0x70: opcode{"BVS", 2, 2, modeNone, buildOpBranch(flagV, true)}, // Extra cycles
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0x90: opcode{"BCC", 2, 2, modeRelative, buildOpBranch(flagC, false)}, // Extra cycles
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0xB0: opcode{"BCS", 2, 2, modeRelative, buildOpBranch(flagC, true)}, // Extra cycles
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0xD0: opcode{"BNE", 2, 2, modeRelative, buildOpBranch(flagZ, false)}, // Extra cycles
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0xF0: opcode{"BEQ", 2, 2, modeRelative, buildOpBranch(flagZ, true)}, // Extra cycles
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0x10: opcode{"BPL", 2, 2, modeRelative, buildOpBranch(flagN, false)}, // Extra cycles
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0x30: opcode{"BMI", 2, 2, modeRelative, buildOpBranch(flagN, true)}, // Extra cycles
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0x50: opcode{"BVC", 2, 2, modeRelative, buildOpBranch(flagV, false)}, // Extra cycles
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0x70: opcode{"BVS", 2, 2, modeRelative, buildOpBranch(flagV, true)}, // Extra cycles
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0xEA: opcode{"NOP", 1, 2, modeNone, opNOP},
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0xEA: opcode{"NOP", 1, 2, modeImplicit, opNOP},
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}
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func executeLine(s *state, line []uint8) {
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@ -503,10 +508,47 @@ func executeLine(s *state, line []uint8) {
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func executeInstruction(s *state) {
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pc := s.registers.getPC()
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opcode := opcodes[s.memory[pc]]
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fmt.Printf("%#04x %s: ", pc, opcode.name)
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pcNext := pc + uint16(opcode.bytes)
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s.registers.setPC(pcNext)
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line := s.memory[pc:pcNext]
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fmt.Printf("%#04x %-10s: ", pc, lineString(s, line, opcode))
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opcode.action(s, line, opcode)
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fmt.Printf("%v, %v\n", s.registers, line)
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fmt.Printf("%v, %x\n", s.registers, line)
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}
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func lineString(s *state, line []uint8, opcode opcode) string {
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t := opcode.name
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switch opcode.addressMode {
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case modeImplicit:
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case modeImplicitX:
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case modeImplicitY:
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//Nothing
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case modeAccumulator:
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t += fmt.Sprintf(" A")
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case modeImmediate:
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t += fmt.Sprintf(" #%02x", line[1])
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case modeZeroPage:
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t += fmt.Sprintf(" $%02x", line[1])
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case modeZeroPageX:
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t += fmt.Sprintf(" $%02x,X", line[1])
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case modeZeroPageY:
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t += fmt.Sprintf(" $%02x,Y", line[1])
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case modeRelative:
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t += fmt.Sprintf(" *%+x", int8(line[1]))
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case modeAbsolute:
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t += fmt.Sprintf(" $%04x", getWordInLine(line))
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case modeAbsoluteX:
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t += fmt.Sprintf(" $%04x,X", getWordInLine(line))
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case modeAbsoluteY:
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t += fmt.Sprintf(" $%04x,X", getWordInLine(line))
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case modeIndirect:
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t += fmt.Sprintf(" ($%04x)", getWordInLine(line))
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case modeIndexedIndirectX:
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t += fmt.Sprintf(" ($%02x,X)", line[1])
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case modeIndirectIndexedY:
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t += fmt.Sprintf(" ($%02x),Y", line[1])
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default:
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t += "UNKNOWN MODE"
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}
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return t
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}
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