Card to bridge PR# and IN# to the host terminal
This commit is contained in:
Ivan Izaguirre
parent
89881a8466
commit
8b50ae1500
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@ -24,11 +24,14 @@ Portable emulator of an Apple II+ or //e. Written in Go.
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- 1Mb Memory Expansion Card (slinky)
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- RAMWorks style expansion Card (up to 16MB additional) (Apple //e only)
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- ThunderClock Plus real time clock
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- Bootable Smartport / ProDOS card
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- Apple //e 80 columns with 64Kb extra RAM and optional RGB modes
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- No Slot Clock based on the DS1216
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- Useful cards not emulating a real card
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- Bootable Smartport / ProDOS card
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- VidHd, limited to the ROM signature and SHR as used by Total Replay, only for //e models with 128Kb
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- FASTChip, limited to what Total Replay needs to set and clear fast mode
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- No Slot Clock based on the DS1216
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- Host console card. Maps the host STDIN and STDOUT to PR# and IN#
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- Graphic modes:
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- Text 40 columns
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- Text 80 columns (Apple //e only)
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@ -164,6 +167,8 @@ Only valid on SDL mode
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```terminal
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-charRom string
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rom file for the character generator (default "<default>")
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-consoleCardSlot int
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slot for the host console card. -1 for none (default -1)
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-disk string
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file to load on the first disk drive (default "<internal>/dos33.dsk")
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-disk2Slot int
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@ -149,10 +149,8 @@ func (a *Apple2) AddMemoryExpansionCard(slot int) {
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}
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// AddThunderClockPlusCard inserts a ThunderClock Plus clock card
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func (a *Apple2) AddThunderClockPlusCard(slot int, romFile string) error {
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c := NewCardThunderClockPlus()
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a.insertCard(c, slot)
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return nil
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func (a *Apple2) AddThunderClockPlusCard(slot int) {
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a.insertCard(NewCardThunderClockPlus(), slot)
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}
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// AddRGBCard inserts an RBG option to the Apple IIe 80 col 64KB card
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@ -75,6 +75,10 @@ func MainApple() *Apple2 {
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"thunderClockCardSlot",
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4,
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"slot for the ThunderClock Plus card. -1 for none")
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consoleCardSlot := flag.Int(
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"consoleCardSlot",
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-1,
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"slot for the host console card. -1 for none")
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nsc := flag.Int(
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"nsc",
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-1,
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@ -235,15 +239,14 @@ func MainApple() *Apple2 {
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a.AddMemoryExpansionCard(*memoryExpansionCardSlot)
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}
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if *thunderClockCardSlot > 0 {
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err := a.AddThunderClockPlusCard(*thunderClockCardSlot,
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"<internal>/ThunderclockPlusROM.bin")
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if err != nil {
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panic(err)
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}
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a.AddThunderClockPlusCard(*thunderClockCardSlot)
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}
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if *vidHDCardSlot >= 0 {
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a.AddVidHD(*vidHDCardSlot)
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}
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if *consoleCardSlot >= 0 {
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a.AddCardInOut(*consoleCardSlot)
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}
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if *smartPortImage != "" {
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err := a.AddSmartPortDisk(5, *smartPortImage, *traceHD)
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@ -294,7 +297,6 @@ func MainApple() *Apple2 {
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}
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// a.AddRomX()
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// a.AddCardInOut(2)
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// a.AddCardLogger(4)
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if *dumpChars {
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197
cardInOut.go
197
cardInOut.go
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@ -1,7 +1,9 @@
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package izapple2
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import (
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"bufio"
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"fmt"
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"os"
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)
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/*
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@ -11,12 +13,15 @@ See:
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"Apple II Monitors peeled."
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http://mysite.du.edu/~etuttle/math/acia.htm
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PR#n stores Cn00 in CSWL and CSWH
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IN#n stores Cn00 in KSWL and KSWH
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*/
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// CardInOut is an experimental card to bridge with the host
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// CardInOut is an experimental card to bridge with the host console
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type CardInOut struct {
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cardBase
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i int
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reader *bufio.Reader
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}
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// NewCardInOut creates CardInOut
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@ -27,129 +32,137 @@ func NewCardInOut() *CardInOut {
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}
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func (c *CardInOut) assign(a *Apple2, slot int) {
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for i := uint8(0x0); i <= 0xf; i++ {
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iCopy := i
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c.addCardSoftSwitchR(i, func(*ioC0Page) uint8 {
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value := []uint8{0xc1, 0xc1, 0x93, 0x0}[c.i%4]
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c.i++
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fmt.Printf("[cardInOut] Read access to softswith 0x%x for slot %v, value %x.\n", iCopy, slot, value)
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//return 0x41 + 0x80
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return []uint8{0x41, 0x41, 0x13}[i%3] + 0x80
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}, "INOUTR")
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c.addCardSoftSwitchW(i, func(_ *ioC0Page, value uint8) {
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fmt.Printf("[cardInOut] Write access to softswith 0x%x for slot %v, value 0x%x.\n", iCopy, slot, value)
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}, "INOUTW")
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}
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c.addCardSoftSwitchR(0, func(*ioC0Page) uint8 {
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if c.reader == nil {
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c.reader = bufio.NewReader(os.Stdin)
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}
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value, err := c.reader.ReadByte()
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in := true
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out := false
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if err != nil {
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panic(err)
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}
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value += 0x80
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if value&0x7f == 10 {
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value = 13 + 0x80
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}
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//fmt.Printf("[cardInOut] Read access to softswith 0x%x for slot %v, value %x.\n", 0, slot, value)
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return value
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}, "INOUTR")
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c.addCardSoftSwitchW(1, func(_ *ioC0Page, value uint8) {
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//fmt.Printf("[cardInOut] Write access to softswith 0x%x for slot %v, value 0x%x: %v, %v.\n", 1, slot, value, value&0x7f, string(value&0x7f))
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if value&0x7f == 13 {
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fmt.Printf("\n")
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} else {
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fmt.Printf("%v", string(value&0x7f))
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}
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}, "INOUTW")
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data := [256]uint8{
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// Register
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0xA9, 0xC2,
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0x85, 0x37,
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0x85, 0x39,
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0xA9, 0x10,
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0x85, 0x36,
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0xA9, 0x15,
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0x85, 0x38,
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0x60, 0xEA,
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0x4c, 0x40, 0xc2, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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// Out char
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0x8D, 0xA1, 0xC0,
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0x60, 0xEA,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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// Get char
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0x91, 0x28,
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0xAD, 0xA0, 0xC0,
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0x60,
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0x48, 0xA5, 0x38, 0xD0, 0x12, 0xA9, 0xC2, 0xC5,
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0x39, 0xD0, 0x0C, 0xAD, 0x50, 0x00, 0x85, 0x38,
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0x68, 0x91, 0x28, 0xAD, 0xA0, 0xC0, 0x60, 0x68,
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0x8D, 0xA1, 0xC0, 0x60,
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}
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if !out {
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// NOP the CSWL,H change
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for _, v := range []uint8{2, 3, 8, 9} {
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data[v] = 0xEA
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}
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}
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c.romCsxx = newMemoryRangeROM(0xC200, data[:], "InOUt card")
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if !in {
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// NOP the KSWL,H change
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for _, v := range []uint8{4, 5, 12, 13} {
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data[v] = 0xEA
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}
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}
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// Fix slot dependant addresses
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data[0x02] = uint8(0xc0 + slot)
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data[0x46] = uint8(0xc0 + slot)
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data[0x54] = uint8(0x80 + slot<<4)
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data[0x59] = uint8(0x81 + slot<<4)
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c.romCsxx = newMemoryRangeROM(0xC200, data[0:255], "InOUt card")
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if slot != 2 {
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// To make it work on other slots, patch C2, A0 and A1
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panic("Assert failed. Only slot 2 supported for the InOut card")
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}
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c.cardBase.assign(a, slot)
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}
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/*
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The ROM code was assembled using https://www.masswerk.at/6502/assembler.html
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We will have $Cn00 as the entry point for CSWL/H. But before doing
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anything we have to check that we are not in $Cn00 because of an IN#.
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To da that we check id KSWL/H is $Cn00, it is it we wif it to INEntry.
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src:
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BASL = $28
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CSWL = $36
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CSWH = $37
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KSWL = $38
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KSWH = $39
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* = $C200
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Register:
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Entry:
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JMP SkipHeader
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* = $C240
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SkipHeader:
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PHA
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LDA *KSWL
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BNE PREntry
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LDA #$C2
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STA *CSWH
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STA *KSWH
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LDA #$10
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STA *CSWL
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LDA #$15
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CMP *KSWH
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BNE PREntry
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FixKSWL:
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LDA <INEntry
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STA *KSWL
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RTS
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NOP
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OutChar:
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STA $C0A1
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RTS
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NOP
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GetChar:
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INEntry:
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PLA
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STA (BASL),Y
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LDA $C0A0
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RTS
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PREntry:
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PLA
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STA $C0A1
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RTS
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assembled as:
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Listing:
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pass 2
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0000 BASL = 0028
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0000 CSWL = 0036
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0000 CSWH = 0037
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0000 KSWL = 0038
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0000 KSWH = 0039
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* = $C200
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C200 REGIST
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C200 LDA #$C2 A9 C2
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C202 STA *CSWH 85 37
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C204 STA *KSWH 85 39
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C206 LDA #$10 A9 10
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C208 STA *CSWL 85 36
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C20A LDA #$15 A9 15
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C20C STA *KSWL 85 38
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C20E RTS 60
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C20F NOP EA
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C210 OUTCHA
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C210 STA $C0A1 8D A1 C0
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C213 RTS 60
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C214 NOP EA
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C215 GETCHA
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C215 STA (BASL),Y 91 28
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C217 LDA $C0A0 AD A0 C0
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C21A RTS
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* = $C200
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C200 ENTRY:
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C200 JMP SKIPHE 4C 40 C2
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object code:
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A9 C2 85 37 85 39 A9 10
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85 36 A9 15 85 38 60 EA
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8D A1 C0 60 EA 91 28 AD
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A0 C0 60
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* = $C240
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C240 SKIPHE
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C240 PHA 48
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C241 LDA *KSWL A5 38
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C243 BNE PRENTR D0 12
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C245 LDA #$C2 A9 C2
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C247 CMP *KSWH C5 39
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C249 BNE PRENTR D0 0C
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C24B FIXKSW
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C24B LDA <INENTR AD 50 00
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C24E STA *KSWL 85 38
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C250 INENTR
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C250 PLA 68
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C251 STA (BASL),Y 91 28
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C253 LDA $C0A0 AD A0 C0
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C256 RTS 60
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C257 PRENTR
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C257 PLA 68
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C258 STA $C0A1 8D A1 C0
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C25B RTS 60
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done.
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Object Code:
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c200:
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4C 40 C2
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c240:
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48 A5 38 D0 12
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A9 C2 C5 39 D0 0C AD 50
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00 85 38 68 91 28 AD A0
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C0 60 68 8D A1 C0 60
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*/
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