Add proper extra cycle when adding an index cross boundaries on memory reads
This commit is contained in:
Ivan Izaguirre
parent
9c89ad4a61
commit
95998ba37d
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@ -61,10 +61,15 @@ func resolveSetValue(s *State, line []uint8, opcode opcode, value uint8) {
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// The value is in memory
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address := resolveAddress(s, line, opcode)
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s.mem.Poke(address, value)
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// On writes, the possible extra cycle crossing page boundaries is
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// always added and already accounted for.
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s.extraCycleCrossingBoundaries = false
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}
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func resolveAddress(s *State, line []uint8, opcode opcode) uint16 {
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var address uint16
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extraCycle := false
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switch opcode.addressMode {
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case modeZeroPage:
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@ -76,18 +81,20 @@ func resolveAddress(s *State, line []uint8, opcode opcode) uint16 {
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case modeAbsolute:
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address = getWordInLine(line)
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case modeAbsoluteX:
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address = getWordInLine(line) + uint16(s.reg.getX())
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base := getWordInLine(line)
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address, extraCycle = addOffset(base, s.reg.getX())
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case modeAbsoluteY:
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address = getWordInLine(line) + uint16(s.reg.getY())
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base := getWordInLine(line)
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address, extraCycle = addOffset(base, s.reg.getY())
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case modeIndexedIndirectX:
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addressAddress := uint8(line[1] + s.reg.getX())
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addressAddress := line[1] + s.reg.getX()
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address = getZeroPageWord(s.mem, addressAddress)
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case modeIndirect:
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addressAddress := getWordInLine(line)
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address = getWord(s.mem, addressAddress)
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case modeIndirectIndexedY:
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address = getZeroPageWord(s.mem, line[1]) +
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uint16(s.reg.getY())
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base := getZeroPageWord(s.mem, line[1])
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address, extraCycle = addOffset(base, s.reg.getY())
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// 65c02 additions
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case modeIndirectZeroPage:
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address = getZeroPageWord(s.mem, line[1])
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@ -96,17 +103,57 @@ func resolveAddress(s *State, line []uint8, opcode opcode) uint16 {
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address = getWord(s.mem, addressAddress)
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case modeRelative:
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// This assumes that PC is already pointing to the next instruction
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address = s.reg.getPC() + uint16(int8(line[1])) // Note: line[1] is signed
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base := s.reg.getPC()
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address, extraCycle = addOffsetRelative(base, line[1])
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case modeZeroPageAndRelative:
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// Two addressing modes combined. We refer to the second one, relative,
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// placed one byte after the zeropage reference
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address = s.reg.getPC() + uint16(int8(line[2])) // Note: line[2] is signed
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base := s.reg.getPC()
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address, extraCycle = addOffsetRelative(base, line[2])
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default:
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panic("Assert failed. Missing addressing mode")
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}
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if extraCycle {
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s.extraCycleCrossingBoundaries = true
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}
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return address
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}
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/*
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Note: extra cycle on reads when crossing page boundaries.
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Only for:
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modeAbsoluteX
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modeAbsoluteY
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modeIndirectIndexedY
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modeRelative
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modeZeroPageAndRelative
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That is when we add a 8 bit offset to a 16 bit base. The reason is
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that if don't have a page crossing the CPU optimizes one cycle assuming
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that the MSB addition won't change. If it does we spend this extra cycle.
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Note that for writes we don't add a cycle in this case. There is no
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optimization that could make a double write. The regular cycle count
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is alwaus the same with no optimization.
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*/
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func addOffset(base uint16, offset uint8) (uint16, bool) {
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dest := base + uint16(offset)
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if (base & 0xff00) != (dest & 0xff00) {
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return dest, true
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}
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return dest, false
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}
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func addOffsetRelative(base uint16, offset uint8) (uint16, bool) {
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dest := base + uint16(int8(offset))
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if (base & 0xff00) != (dest & 0xff00) {
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return dest, true
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}
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return dest, false
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}
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func lineString(line []uint8, opcode opcode) string {
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t := opcode.name
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switch opcode.addressMode {
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@ -73,18 +73,18 @@ var opcodes65c02Delta = [256]opcode{
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0x65: {"ADC", 2, 3, modeZeroPage, opADCAlt},
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0x75: {"ADC", 2, 4, modeZeroPageX, opADCAlt},
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0x6D: {"ADC", 3, 4, modeAbsolute, opADCAlt},
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0x7D: {"ADC", 3, 4, modeAbsoluteX, opADCAlt},
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0x79: {"ADC", 3, 4, modeAbsoluteY, opADCAlt},
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0x7D: {"ADC", 3, 4, modeAbsoluteX, opADCAlt}, // Extra cycles
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0x79: {"ADC", 3, 4, modeAbsoluteY, opADCAlt}, // Extra cycles
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0x61: {"ADC", 2, 6, modeIndexedIndirectX, opADCAlt},
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0x71: {"ADC", 2, 5, modeIndirectIndexedY, opADCAlt},
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0x71: {"ADC", 2, 5, modeIndirectIndexedY, opADCAlt}, // Extra cycles
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0xE9: {"SBC", 2, 2, modeImmediate, opSBCAlt},
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0xE5: {"SBC", 2, 3, modeZeroPage, opSBCAlt},
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0xF5: {"SBC", 2, 4, modeZeroPageX, opSBCAlt},
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0xED: {"SBC", 3, 4, modeAbsolute, opSBCAlt},
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0xFD: {"SBC", 3, 4, modeAbsoluteX, opSBCAlt},
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0xF9: {"SBC", 3, 4, modeAbsoluteY, opSBCAlt},
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0xFD: {"SBC", 3, 4, modeAbsoluteX, opSBCAlt}, // Extra cycles
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0xF9: {"SBC", 3, 4, modeAbsoluteY, opSBCAlt}, // Extra cycles
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0xE1: {"SBC", 2, 6, modeIndexedIndirectX, opSBCAlt},
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0xF1: {"SBC", 2, 5, modeIndirectIndexedY, opSBCAlt},
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0xF1: {"SBC", 2, 5, modeIndirectIndexedY, opSBCAlt}, // Extra cycles
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// Different cycle count
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0x1e: {"ASL", 3, 6, modeAbsoluteX, buildOpShift(true, false)},
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@ -105,7 +105,7 @@ var opcodes65c02Delta = [256]opcode{
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// New addressing options
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0x89: {"BIT", 2, 2, modeImmediate, opBIT},
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0x34: {"BIT", 2, 4, modeZeroPageX, opBIT},
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0x3c: {"BIT", 3, 4, modeAbsoluteX, opBIT},
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0x3c: {"BIT", 3, 4, modeAbsoluteX, opBIT}, // Extra cycles
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0x1a: {"INC", 1, 2, modeAccumulator, buildOpIncDec(true)},
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0x3a: {"DEC", 1, 2, modeAccumulator, buildOpIncDec(false)},
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0x7c: {"JMP", 3, 6, modeAbsoluteIndexedIndirectX, opJMP},
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@ -115,7 +115,7 @@ var opcodes65c02Delta = [256]opcode{
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0x5a: {"PHY", 1, 3, modeImplicit, buildOpPush(regY)},
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0xfa: {"PLX", 1, 4, modeImplicit, buildOpPull(regX)},
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0x7a: {"PLY", 1, 4, modeImplicit, buildOpPull(regY)},
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0x80: {"BRA", 2, 4, modeRelative, opJMP},
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0x80: {"BRA", 2, 4, modeRelative, opJMP}, // Extra cycles
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0x64: {"STZ", 2, 3, modeZeroPage, opSTZ},
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0x74: {"STZ", 2, 4, modeZeroPageX, opSTZ},
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@ -130,22 +130,22 @@ var opcodes65c02Delta = [256]opcode{
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// Additional in Rockwell 65c02 and WDC 65c02?
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// They have a double addressing mode: zeropage and relative.
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0x0f: {"BBR0", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(0, false)},
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0x1f: {"BBR1", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(1, false)},
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0x2f: {"BBR2", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(2, false)},
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0x3f: {"BBR3", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(3, false)},
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0x4f: {"BBR4", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(4, false)},
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0x5f: {"BBR5", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(5, false)},
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0x6f: {"BBR6", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(6, false)},
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0x7f: {"BBR7", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(7, false)},
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0x8f: {"BBS0", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(0, true)},
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0x9f: {"BBS1", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(1, true)},
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0xaf: {"BBS2", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(2, true)},
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0xbf: {"BBS3", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(3, true)},
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0xcf: {"BBS4", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(4, true)},
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0xdf: {"BBS5", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(5, true)},
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0xef: {"BBS6", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(6, true)},
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0xff: {"BBS7", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(7, true)},
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0x0f: {"BBR0", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(0, false)}, // Extra cycles
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0x1f: {"BBR1", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(1, false)}, // Extra cycles
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0x2f: {"BBR2", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(2, false)}, // Extra cycles
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0x3f: {"BBR3", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(3, false)}, // Extra cycles
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0x4f: {"BBR4", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(4, false)}, // Extra cycles
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0x5f: {"BBR5", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(5, false)}, // Extra cycles
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0x6f: {"BBR6", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(6, false)}, // Extra cycles
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0x7f: {"BBR7", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(7, false)}, // Extra cycles
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0x8f: {"BBS0", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(0, true)}, // Extra cycles
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0x9f: {"BBS1", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(1, true)}, // Extra cycles
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0xaf: {"BBS2", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(2, true)}, // Extra cycles
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0xbf: {"BBS3", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(3, true)}, // Extra cycles
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0xcf: {"BBS4", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(4, true)}, // Extra cycles
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0xdf: {"BBS5", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(5, true)}, // Extra cycles
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0xef: {"BBS6", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(6, true)}, // Extra cycles
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0xff: {"BBS7", 3, 2, modeZeroPageAndRelative, buildOpBranchOnBit(7, true)}, // Extra cycles
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0x07: {"RMB0", 2, 5, modeZeroPage, buildOpSetBit(0, false)},
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0x17: {"RMB1", 2, 5, modeZeroPage, buildOpSetBit(1, false)},
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@ -24,8 +24,9 @@ type State struct {
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mem Memory
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cycles uint64
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extraCycle bool
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lineCache []uint8
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extraCycleCrossingBoundaries bool
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extraCycleBranchTaken bool
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lineCache []uint8
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// We cache the allocation of a line to avoid a malloc per instruction. To be used only
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// by ExecuteInstruction(). 2x speedup on the emulation!!
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}
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@ -79,10 +80,16 @@ func (s *State) ExecuteInstruction() {
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}
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opcode.action(s, s.lineCache, opcode)
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s.cycles += uint64(opcode.cycles)
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if s.extraCycle {
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if s.extraCycleBranchTaken {
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s.cycles++
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s.extraCycle = false
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s.extraCycleBranchTaken = false
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}
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if s.extraCycleCrossingBoundaries {
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s.cycles++
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s.extraCycleCrossingBoundaries = false
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}
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if s.trace {
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fmt.Printf("%v, [%02x]\n", s.reg, s.lineCache[0:opcode.bytes])
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}
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@ -76,7 +76,7 @@ func buildOpUpdateFlag(flag uint8, value bool) opFunc {
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func buildOpBranch(flag uint8, test bool) opFunc {
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return func(s *State, line []uint8, opcode opcode) {
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if s.reg.getFlag(flag) == test {
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s.extraCycle = true
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s.extraCycleBranchTaken = true
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address := resolveAddress(s, line, opcode)
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s.reg.setPC(address)
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}
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@ -92,6 +92,7 @@ func buildOpBranchOnBit(bit uint8, test bool) opFunc {
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bitValue := ((value >> bit) & 1) == 1
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if bitValue == test {
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s.extraCycleBranchTaken = true
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address := resolveAddress(s, line, opcode)
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s.reg.setPC(address)
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}
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