From 964f5bc3bec0f0f83d4dccc944198eb2cd3b7972 Mon Sep 17 00:00:00 2001 From: Ivan Izaguirre Date: Mon, 28 Jan 2019 23:40:18 +0100 Subject: [PATCH] Added INC and DEC --- execute.go | 109 +++++++++++++++++++++++++++++++++------------------ registers.go | 13 +++--- 2 files changed, 78 insertions(+), 44 deletions(-) diff --git a/execute.go b/execute.go index fe2e303..3ae67fe 100644 --- a/execute.go +++ b/execute.go @@ -20,6 +20,8 @@ const modeAbsoluteY = 5 const modeIndexedIndirectX = 7 const modeIndirectIndexedY = 8 const modeAccumulator = 9 +const modeRegisterX = 10 +const modeRegisterY = 11 // https://www.masswerk.at/6502/6502_instruction_set.html // http://www.emulator101.com/reference/6502-reference.html @@ -50,25 +52,46 @@ func buildOpTransfer(regSrc int, regDst int) opFunc { } } -func buildOpIncDecRegister(reg int, inc bool) opFunc { +func buildOpIncDec(addressMode int, inc bool) opFunc { return func(s *state, line []uint8, opcode opcode) { - value := s.registers.getRegister(reg) + value, hasAddress, address, register := resolveWithAddressMode(s, line, addressMode) if inc { value++ } else { value-- } - s.registers.setRegister(reg, value) s.registers.updateFlagZN(value) + storeWhereNeeded(s, value, hasAddress, address, register) } } -func resolveWithAddressMode(s *state, line []uint8, addressMode int) (value uint8, hasAddress bool, address uint16) { +func storeWhereNeeded(s *state, value uint8, hasAddress bool, address uint16, register int) { + if hasAddress { + s.memory[address] = value + } else if register != regNone { + s.registers.setRegister(register, value) + } else { + // Todo: assert impossible + } +} + +func resolveWithAddressMode(s *state, line []uint8, addressMode int) ( + value uint8, hasAddress bool, address uint16, register int) { hasAddress = true + register = regNone switch addressMode { case modeAccumulator: value = s.registers.getA() hasAddress = false + register = regA + case modeRegisterX: + value = s.registers.getX() + hasAddress = false + register = regX + case modeRegisterY: + value = s.registers.getY() + hasAddress = false + register = regY case modeImmediate: value = line[1] hasAddress = false @@ -100,7 +123,7 @@ func resolveWithAddressMode(s *state, line []uint8, addressMode int) (value uint func buildRotate(addressMode int, isLeft bool) opFunc { return func(s *state, line []uint8, opcode opcode) { - value, hasAddress, address := resolveWithAddressMode(s, line, addressMode) + value, hasAddress, address, register := resolveWithAddressMode(s, line, addressMode) oldCarry := s.registers.getFlagBit(flagC) var carry bool @@ -115,64 +138,74 @@ func buildRotate(addressMode int, isLeft bool) opFunc { } s.registers.updateFlag(flagC, carry) s.registers.updateFlagZN(value) - - if hasAddress { - s.memory[address] = value - } else { - s.registers.setA(value) - } + storeWhereNeeded(s, value, hasAddress, address, register) } } func buildOpLoad(addressMode int, regDst int) opFunc { return func(s *state, line []uint8, opcode opcode) { - value, _, _ := resolveWithAddressMode(s, line, addressMode) + value, _, _, _ := resolveWithAddressMode(s, line, addressMode) s.registers.setRegister(regDst, value) s.registers.updateFlagZN(value) } } var opcodes = [256]opcode{ - 0x26: opcode{"ROL", 2, 5, buildRotate(modeZeroPage, true)}, 0x2A: opcode{"ROL", 1, 2, buildRotate(modeAccumulator, true)}, - 0x2E: opcode{"ROL", 3, 6, buildRotate(modeAbsolute, true)}, + 0x26: opcode{"ROL", 2, 5, buildRotate(modeZeroPage, true)}, 0x36: opcode{"ROL", 2, 6, buildRotate(modeZeroPageX, true)}, + 0x2E: opcode{"ROL", 3, 6, buildRotate(modeAbsolute, true)}, 0x3E: opcode{"ROL", 3, 7, buildRotate(modeAbsoluteX, true)}, - 0x66: opcode{"ROR", 2, 5, buildRotate(modeZeroPage, false)}, 0x6A: opcode{"ROR", 1, 2, buildRotate(modeAccumulator, false)}, - 0x6E: opcode{"ROR", 3, 6, buildRotate(modeAbsolute, false)}, + 0x66: opcode{"ROR", 2, 5, buildRotate(modeZeroPage, false)}, 0x76: opcode{"ROR", 2, 6, buildRotate(modeZeroPageX, false)}, + 0x6E: opcode{"ROR", 3, 6, buildRotate(modeAbsolute, false)}, 0x7E: opcode{"ROR", 3, 7, buildRotate(modeAbsoluteX, false)}, - 0x88: opcode{"DEY", 1, 2, buildOpIncDecRegister(regY, false)}, + 0xE6: opcode{"INC", 2, 5, buildOpIncDec(modeZeroPage, true)}, + 0xF6: opcode{"INC", 2, 6, buildOpIncDec(modeZeroPageX, true)}, + 0xEE: opcode{"INC", 3, 6, buildOpIncDec(modeAbsolute, true)}, + 0xFE: opcode{"INC", 3, 7, buildOpIncDec(modeAbsoluteX, true)}, + + 0xC6: opcode{"DEC", 2, 5, buildOpIncDec(modeZeroPage, false)}, + 0xD6: opcode{"DEC", 2, 6, buildOpIncDec(modeZeroPageX, false)}, + 0xCE: opcode{"DEC", 3, 6, buildOpIncDec(modeAbsolute, false)}, + 0xDE: opcode{"DEC", 3, 7, buildOpIncDec(modeAbsoluteX, false)}, + + 0xE8: opcode{"INX", 1, 2, buildOpIncDec(modeRegisterX, true)}, + 0xC8: opcode{"INY", 1, 2, buildOpIncDec(modeRegisterY, true)}, + 0xCA: opcode{"DEX", 1, 2, buildOpIncDec(modeRegisterX, false)}, + 0x88: opcode{"DEY", 1, 2, buildOpIncDec(modeRegisterY, false)}, + + 0xAA: opcode{"TAX", 1, 2, buildOpTransfer(regA, regX)}, + 0xA8: opcode{"TAY", 1, 2, buildOpTransfer(regA, regY)}, 0x8A: opcode{"TXA", 1, 2, buildOpTransfer(regX, regA)}, 0x98: opcode{"TYA", 1, 2, buildOpTransfer(regY, regA)}, 0x9A: opcode{"TXS", 1, 2, buildOpTransfer(regX, regSP)}, - 0xA0: opcode{"LDY", 2, 2, buildOpLoad(modeImmediate, regY)}, - 0xA1: opcode{"LDX", 2, 6, buildOpLoad(modeIndexedIndirectX, regA)}, - 0xA2: opcode{"LDX", 2, 2, buildOpLoad(modeImmediate, regX)}, - 0xA4: opcode{"LDY", 2, 3, buildOpLoad(modeZeroPage, regY)}, - 0xA5: opcode{"LDA", 2, 3, buildOpLoad(modeZeroPage, regA)}, - 0xA6: opcode{"LDX", 2, 3, buildOpLoad(modeZeroPage, regX)}, - 0xA8: opcode{"TAY", 1, 2, buildOpTransfer(regA, regY)}, - 0xA9: opcode{"LDA", 2, 2, buildOpLoad(modeImmediate, regA)}, - 0xAA: opcode{"TAX", 1, 2, buildOpTransfer(regA, regX)}, - 0xAC: opcode{"LDY", 3, 4, buildOpLoad(modeAbsolute, regY)}, - 0xAD: opcode{"LDA", 3, 4, buildOpLoad(modeAbsolute, regA)}, - 0xAE: opcode{"LDX", 3, 4, buildOpLoad(modeAbsolute, regX)}, - 0xB1: opcode{"LDX", 2, 5, buildOpLoad(modeIndirectIndexedY, regA)}, // Extra cycles - 0xB4: opcode{"LDY", 2, 4, buildOpLoad(modeZeroPageX, regY)}, - 0xB5: opcode{"LDA", 2, 4, buildOpLoad(modeZeroPageX, regA)}, - 0xB6: opcode{"LDX", 2, 4, buildOpLoad(modeZeroPageY, regX)}, - 0xB9: opcode{"LDA", 3, 4, buildOpLoad(modeAbsoluteY, regA)}, // Extra cycles 0xBA: opcode{"TSX", 1, 2, buildOpTransfer(regSP, regX)}, - 0xBC: opcode{"LDY", 3, 4, buildOpLoad(modeAbsoluteX, regY)}, // Extra cycles + + 0xA9: opcode{"LDA", 2, 2, buildOpLoad(modeImmediate, regA)}, + 0xA5: opcode{"LDA", 2, 3, buildOpLoad(modeZeroPage, regA)}, + 0xB5: opcode{"LDA", 2, 4, buildOpLoad(modeZeroPageX, regA)}, + 0xAD: opcode{"LDA", 3, 4, buildOpLoad(modeAbsolute, regA)}, 0xBD: opcode{"LDA", 3, 4, buildOpLoad(modeAbsoluteX, regA)}, // Extra cycles + 0xB9: opcode{"LDA", 3, 4, buildOpLoad(modeAbsoluteY, regA)}, // Extra cycles + + 0xA2: opcode{"LDX", 2, 2, buildOpLoad(modeImmediate, regX)}, + 0xA6: opcode{"LDX", 2, 3, buildOpLoad(modeZeroPage, regX)}, + 0xB6: opcode{"LDX", 2, 4, buildOpLoad(modeZeroPageY, regX)}, + 0xAE: opcode{"LDX", 3, 4, buildOpLoad(modeAbsolute, regX)}, 0xBE: opcode{"LDX", 3, 4, buildOpLoad(modeAbsoluteY, regX)}, // Extra cycles - 0xC8: opcode{"INY", 1, 2, buildOpIncDecRegister(regY, true)}, - 0xCA: opcode{"DEX", 1, 2, buildOpIncDecRegister(regX, false)}, - 0xE8: opcode{"INX", 1, 2, buildOpIncDecRegister(regX, true)}, + 0xA1: opcode{"LDX", 2, 6, buildOpLoad(modeIndexedIndirectX, regA)}, + 0xB1: opcode{"LDX", 2, 5, buildOpLoad(modeIndirectIndexedY, regA)}, // Extra cycles + + 0xA0: opcode{"LDY", 2, 2, buildOpLoad(modeImmediate, regY)}, + 0xA4: opcode{"LDY", 2, 3, buildOpLoad(modeZeroPage, regY)}, + 0xB4: opcode{"LDY", 2, 4, buildOpLoad(modeZeroPageX, regY)}, + 0xAC: opcode{"LDY", 3, 4, buildOpLoad(modeAbsolute, regY)}, + 0xBC: opcode{"LDY", 3, 4, buildOpLoad(modeAbsoluteX, regY)}, // Extra cycles + 0xEA: opcode{"NOP", 1, 2, opNOP}, } diff --git a/registers.go b/registers.go index a589176..f0bd4f6 100644 --- a/registers.go +++ b/registers.go @@ -3,12 +3,13 @@ package main import "fmt" const ( - regA = 0 - regX = 1 - regY = 2 - regP = 4 - regSP = 5 - regPC = 6 // 2 bytes + regA = 0 + regX = 1 + regY = 2 + regP = 4 + regSP = 5 + regPC = 6 // 2 bytes + regNone = -1 ) const (