Incomplete Smartport implementation. Not really needed for Total Replay
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@ -73,8 +73,6 @@ casa@servidor:~$ ./apple2sdl -hd "Total Replay v2.0.2mg"
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```
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```
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Displays super hi-res box art as seen with the VidHD card.
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Displays super hi-res box art as seen with the VidHD card.
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Note: for version 3, compile `4cade` with `use_smartport = 0` in `prorwts2.a` as SmartPort is not emulated (yet).
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![Total Replay](doc/totalreplay.png)
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![Total Replay](doc/totalreplay.png)
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### Terminal mode
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### Terminal mode
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@ -4,10 +4,13 @@ import "fmt"
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/*
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/*
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To implement a hard drive we just have to support boot from #PR7 and the PRODOS expextations.
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To implement a hard drive we just have to support boot from #PR7 and the PRODOS expextations.
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See Beneath Prodos, section 6-6, 7-13 and 5-8. (http://www.apple-iigs.info/doc/fichiers/beneathprodos.pdf)
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See:
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See:
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Beneath Prodos, section 6-6, 7-13 and 5-8. (http://www.apple-iigs.info/doc/fichiers/beneathprodos.pdf)
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Apple IIc Technical Reference, 2nd Edition. Chapter 8. https://ia800207.us.archive.org/19/items/AppleIIcTechnicalReference2ndEd/Apple%20IIc%20Technical%20Reference%202nd%20ed.pdf
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https://prodos8.com/docs/technote/21/
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https://prodos8.com/docs/technote/21/
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*/
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*/
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type cardHardDisk struct {
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type cardHardDisk struct {
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@ -23,13 +26,13 @@ func buildHardDiskRom(slot int) []uint8 {
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copy(data, []uint8{
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copy(data, []uint8{
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// Preamble bytes to comply with the expectation in $Cn01, 3, 5 and 7
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// Preamble bytes to comply with the expectation in $Cn01, 3, 5 and 7
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0xa9, 0x20, // LDA #$20
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0xa9, 0x20, // LDA #$20
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0xa9, 0x00, // LDA #$20
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0xa9, 0x00, // LDA #$00
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0xa9, 0x03, // LDA #$20
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0xa9, 0x03, // LDA #$03
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0xa9, 0x3c, // LDA #$3c
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0xa9, 0x3c, // LDA #$3c
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// Alternate: 0xa9, 0x00, // LDA #$00 ; Not a Smartport device, but won't boot on ii+ ROM
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// Alternate: 0xa9, 0x00, // LDA #$00 ; Not a Smartport device, but won't boot on ii+ ROM
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// Boot code: SS will load block 0 in address $0800. The jump there.
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// Boot code: SS will load block 0 in address $0800. The jump there.
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// Note: on execution the first block expects $42 to $47 to have
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// Note: after execution the first block expects $42 to $47 to have
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// valid values to read block 0. At least Total Replay expects that.
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// valid values to read block 0. At least Total Replay expects that.
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0xa9, 0x01, // LDA·#$01
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0xa9, 0x01, // LDA·#$01
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0x85, 0x42, // STA $42 ; Command READ(1)
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0x85, 0x42, // STA $42 ; Command READ(1)
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@ -42,15 +45,37 @@ func buildHardDiskRom(slot int) []uint8 {
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0x85, 0x45, // STA $45 ; Dest HI($0800)
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0x85, 0x45, // STA $45 ; Dest HI($0800)
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0xad, ssBase, 0xc0, // LDA $C0n1 ;Call to softswitch 0.
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0xad, ssBase, 0xc0, // LDA $C0n1 ;Call to softswitch 0.
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0xa2, uint8(slot << 4), // LDX $s7 ;Slot on hign nibble of X
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0xa2, uint8(slot << 4), // LDX $s7 ; Slot on hign nibble of X
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0x4c, 0x01, 0x08, // JMP $801
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0x4c, 0x01, 0x08, // JMP $801 ; Jump to loaded boot sector
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})
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})
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// Entrypoints and Smartport body
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copy(data[0x40:], []uint8{
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0x4c, 0x80, 0xc0 + uint8(slot), // JMP $cs80 ; Prodos Entrypoint
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// 3 btes later, smartport entrypoint. Uses the ProDos MLI calling convention
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0x68, // PLA
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0x8d, ssBase + 4, 0xc0, // STA $c0n4 ; Softswitch 4, store LO(cmdblock)
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0xa8, // TAY ; We will need it later
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0x68, // PLA
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0x8d, ssBase + 5, 0xc0, // STA $c0n5 ; Softswitch 5, store HI(cmdblock)
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0x48, // PHA
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0x98, // TYA
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0x69, 0x03, // ADC #$03 ; Fix return address past the cmdblock
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0x48, // PHA
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0xad, ssBase + 3, 0xc0, // LDA $C0n3 ; Softswitch 3, execute command. Error code in reg A.
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0x18, // CLC ; Clear carry for no errors.
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0xF0, 0x01, // BEQ $01 ; Skips the SEC if reg A is zero
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0x38, // SEC ; Set carry on errors
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0x60, // RTS
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})
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// Prodos entrypoint body
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copy(data[0x80:], []uint8{
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copy(data[0x80:], []uint8{
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0xad, ssBase + 0, 0xc0, // LDA $C0n0 ; Softswitch 0, execute command. Error code in reg A.
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0xad, ssBase + 0, 0xc0, // LDA $C0n0 ; Softswitch 0, execute command. Error code in reg A.
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0x48, // PHA
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0x48, // PHA
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0xae, ssBase + 1, 0xc0, // LDX $C0n1 ; Softswitch 2, LO(Blocks), STATUS needs that in reg X.
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0xae, ssBase + 1, 0xc0, // LDX $C0n1 ; Softswitch 1, LO(Blocks), STATUS needs that in reg X.
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0xac, ssBase + 2, 0xc0, // LDY $C0n2 ; Softswitch 3, HI(Blocks). STATUS needs that in reg Y.
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0xac, ssBase + 2, 0xc0, // LDY $C0n2 ; Softswitch 2, HI(Blocks). STATUS needs that in reg Y.
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0x18, // CLC ; Clear carry for no errors.
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0x18, // CLC ; Clear carry for no errors.
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0x68, // PLA ; Sets Z if no error
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0x68, // PLA ; Sets Z if no error
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0xF0, 0x01, // BEQ $01 ; Skips the SEC if reg A is zero
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0xF0, 0x01, // BEQ $01 ; Skips the SEC if reg A is zero
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@ -61,7 +86,7 @@ func buildHardDiskRom(slot int) []uint8 {
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data[0xfc] = 0
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data[0xfc] = 0
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data[0xfd] = 0
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data[0xfd] = 0
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data[0xfe] = 3 // Status and Read. No write, no format. Single volume
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data[0xfe] = 3 // Status and Read. No write, no format. Single volume
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data[0xff] = 0x80 // Driver entry point
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data[0xff] = 0x40 // Driver entry point
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return data
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return data
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}
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}
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@ -113,6 +138,19 @@ func (c *cardHardDisk) assign(a *Apple2, slot int) {
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return uint8(c.disk.header.Blocks >> 8)
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return uint8(c.disk.header.Blocks >> 8)
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}, "HDBLOCKHI")
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}, "HDBLOCKHI")
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c.addCardSoftSwitchR(3, func(*ioC0Page) uint8 {
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if c.trace {
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fmt.Printf("[CardHardDisk] Smart port command. Not implemented.\n")
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}
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return proDosDeviceErrorIO
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}, "HDSMARTPORT")
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c.addCardSoftSwitchW(4, func(*ioC0Page, uint8) {
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// Not implemented
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}, "HDSMARTPORTLO")
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c.addCardSoftSwitchW(5, func(*ioC0Page, uint8) {
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// Not implemented
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}, "HDSMARTPORTHI")
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c.cardBase.assign(a, slot)
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c.cardBase.assign(a, slot)
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}
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}
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