Fix a2audit regression on aux mem

2020-09-23 18:21:45 +02:00 · 2020-09-23 18:21:45 +02:00 · 9ce9d1f96d
parent 8ebd745a63
commit 9ce9d1f96d
1 changed files with 1 additions and 0 deletions
--- a/memoryManager.go
+++ b/memoryManager.go
@ -188,6 +188,7 @@ func (mmu *memoryManager) accessWrite(address uint16) memoryHandler {
 		return mmu.getPhysicalMainRAM(mmu.altMainRAMActiveWrite)
 	}
 	if address <= addressLimitIO {
+		mmu.lastAddressPage = invalidAddressPage
 		return mmu.apple2.io
 	}
 	if address <= addressLimitSlotsExtra {