Fix a2audit regression on aux mem
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@ -188,6 +188,7 @@ func (mmu *memoryManager) accessWrite(address uint16) memoryHandler {
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return mmu.getPhysicalMainRAM(mmu.altMainRAMActiveWrite)
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return mmu.getPhysicalMainRAM(mmu.altMainRAMActiveWrite)
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}
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}
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if address <= addressLimitIO {
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if address <= addressLimitIO {
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mmu.lastAddressPage = invalidAddressPage
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return mmu.apple2.io
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return mmu.apple2.io
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}
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}
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if address <= addressLimitSlotsExtra {
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if address <= addressLimitSlotsExtra {
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