diff --git a/execute.go b/execute.go
index a75c1c8..2074277 100644
--- a/execute.go
+++ b/execute.go
@@ -40,7 +40,7 @@ type opFunc func(s *state, line []uint8, opcode opcode)
 
 func opNOP(s *state, line []uint8, opcode opcode) {}
 
-func buildOPTransfer(regSrc int, regDst int) opFunc {
+func buildOpTransfer(regSrc int, regDst int) opFunc {
 	return func(s *state, line []uint8, opcode opcode) {
 		value := s.registers.getRegister(regSrc)
 		s.registers.setRegister(regDst, value)
@@ -125,58 +125,38 @@ func buildOpLoad(addressMode int, regDst int) opFunc {
 
 var opcodes = [256]opcode{
 	0x26: opcode{"ROL", 2, 5, buildRotateLeft(modeZeroPage)},
-
 	0x2A: opcode{"ROL", 1, 2, buildRotateLeft(modeAccumulator)},
-
 	0x2E: opcode{"ROL", 3, 6, buildRotateLeft(modeAbsolute)},
-
 	0x36: opcode{"ROL", 2, 6, buildRotateLeft(modeZeroPageX)},
-
 	0x3E: opcode{"ROL", 3, 7, buildRotateLeft(modeAbsoluteX)},
-
 	0x88: opcode{"DEY", 1, 2, buildOpIncDecRegister(regY, false)},
-
-	0x8A: opcode{"TXA", 1, 2, buildOPTransfer(regX, regA)},
-
-	0x98: opcode{"TYA", 1, 2, buildOPTransfer(regY, regA)},
-
-	0x9A: opcode{"TXS", 1, 2, buildOPTransfer(regX, regSP)},
-
+	0x8A: opcode{"TXA", 1, 2, buildOpTransfer(regX, regA)},
+	0x98: opcode{"TYA", 1, 2, buildOpTransfer(regY, regA)},
+	0x9A: opcode{"TXS", 1, 2, buildOpTransfer(regX, regSP)},
 	0xA0: opcode{"LDY", 2, 2, buildOpLoad(modeImmediate, regY)},
 	0xA1: opcode{"LDX", 2, 6, buildOpLoad(modeIndexedIndirectX, regA)},
 	0xA2: opcode{"LDX", 2, 2, buildOpLoad(modeImmediate, regX)},
-
 	0xA4: opcode{"LDY", 2, 3, buildOpLoad(modeZeroPage, regY)},
 	0xA5: opcode{"LDA", 2, 3, buildOpLoad(modeZeroPage, regA)},
 	0xA6: opcode{"LDX", 2, 3, buildOpLoad(modeZeroPage, regX)},
-
-	0xA8: opcode{"TAY", 1, 2, buildOPTransfer(regA, regY)},
+	0xA8: opcode{"TAY", 1, 2, buildOpTransfer(regA, regY)},
 	0xA9: opcode{"LDA", 2, 2, buildOpLoad(modeImmediate, regA)},
-	0xAA: opcode{"TAX", 1, 2, buildOPTransfer(regA, regX)},
-
+	0xAA: opcode{"TAX", 1, 2, buildOpTransfer(regA, regX)},
 	0xAC: opcode{"LDY", 3, 4, buildOpLoad(modeAbsolute, regY)},
 	0xAD: opcode{"LDA", 3, 4, buildOpLoad(modeAbsolute, regA)},
 	0xAE: opcode{"LDX", 3, 4, buildOpLoad(modeAbsolute, regX)},
-
 	0xB1: opcode{"LDX", 2, 5, buildOpLoad(modeIndirectIndexedY, regA)}, // Extra cycles
-
 	0xB4: opcode{"LDY", 2, 4, buildOpLoad(modeZeroPageX, regY)},
 	0xB5: opcode{"LDA", 2, 4, buildOpLoad(modeZeroPageX, regA)},
 	0xB6: opcode{"LDX", 2, 4, buildOpLoad(modeZeroPageY, regX)},
-
 	0xB9: opcode{"LDA", 3, 4, buildOpLoad(modeAbsoluteY, regA)}, // Extra cycles
-	0xBA: opcode{"TSX", 1, 2, buildOPTransfer(regSP, regX)},
-
+	0xBA: opcode{"TSX", 1, 2, buildOpTransfer(regSP, regX)},
 	0xBC: opcode{"LDY", 3, 4, buildOpLoad(modeAbsoluteX, regY)}, // Extra cycles
 	0xBD: opcode{"LDA", 3, 4, buildOpLoad(modeAbsoluteX, regA)}, // Extra cycles
 	0xBE: opcode{"LDX", 3, 4, buildOpLoad(modeAbsoluteY, regX)}, // Extra cycles
-
 	0xC8: opcode{"INY", 1, 2, buildOpIncDecRegister(regY, true)},
-
 	0xCA: opcode{"DEX", 1, 2, buildOpIncDecRegister(regX, false)},
-
 	0xE8: opcode{"INX", 1, 2, buildOpIncDecRegister(regX, true)},
-
 	0xEA: opcode{"NOP", 1, 2, opNOP},
 }