Added the six transfer opcodes
This commit is contained in:
Ivan Izaguirre
parent
ba1053c1ac
commit
d376e46596
122
execute.go
122
execute.go
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@ -30,8 +30,6 @@ type opcode struct {
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name string
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bytes int
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cycles int
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mode int
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reg int
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action opFunc
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}
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@ -39,71 +37,87 @@ type opFunc func(s *state, line []uint8, opcode opcode)
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func opNOP(s *state, line []uint8, opcode opcode) {}
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func opLDR(s *state, line []uint8, opcode opcode) {
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var value uint8
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switch opcode.mode {
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case modeImmediate:
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value = line[1]
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case modeZeroPage:
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address := line[1]
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value = s.memory[address]
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case modeZeroPageX:
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address := line[1] + s.registers.getX()
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value = s.memory[address]
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case modeZeroPageY:
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address := line[1] + s.registers.getY()
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value = s.memory[address]
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case modeAbsolute:
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address := getWordInLine(line)
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value = s.memory[address]
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case modeAbsoluteX:
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address := getWordInLine(line) + uint16(s.registers.getX())
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value = s.memory[address]
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case modeAbsoluteY:
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address := getWordInLine(line) + uint16(s.registers.getY())
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value = s.memory[address]
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case modeIndexedIndirectX:
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addressAddress := uint8(line[1] + s.registers.getX())
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address := s.memory.getZeroPageWord(addressAddress)
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value = s.memory[address]
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case modeIndirectIndexedY:
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address := s.memory.getZeroPageWord(line[1]) +
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uint16(s.registers.getY())
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value = s.memory[address]
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func buildOPTransfer(regSrc int, regDst int) opFunc {
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return func(s *state, line []uint8, opcode opcode) {
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s.registers.setRegister(regDst, s.registers.getRegister(regSrc))
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// TODO: Update flags (N, Z) for all but TXS
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}
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}
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s.registers.setRegister(opcode.reg, value)
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func buildOpLoad(addressMode int, regDst int) opFunc {
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return func(s *state, line []uint8, opcode opcode) {
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var value uint8
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switch addressMode {
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case modeImmediate:
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value = line[1]
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case modeZeroPage:
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address := line[1]
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value = s.memory[address]
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case modeZeroPageX:
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address := line[1] + s.registers.getX()
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value = s.memory[address]
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case modeZeroPageY:
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address := line[1] + s.registers.getY()
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value = s.memory[address]
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case modeAbsolute:
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address := getWordInLine(line)
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value = s.memory[address]
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case modeAbsoluteX:
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address := getWordInLine(line) + uint16(s.registers.getX())
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value = s.memory[address]
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case modeAbsoluteY:
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address := getWordInLine(line) + uint16(s.registers.getY())
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value = s.memory[address]
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case modeIndexedIndirectX:
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addressAddress := uint8(line[1] + s.registers.getX())
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address := s.memory.getZeroPageWord(addressAddress)
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value = s.memory[address]
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case modeIndirectIndexedY:
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address := s.memory.getZeroPageWord(line[1]) +
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uint16(s.registers.getY())
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value = s.memory[address]
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}
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// TODO: Update flags (N, Z)
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s.registers.setRegister(regDst, value)
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// TODO: Update flags (N, Z)
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}
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}
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var opcodes = [256]opcode{
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0x00: opcode{"BRK", 1, 7, modeImmediate, regNone, opNOP},
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0x00: opcode{"BRK", 1, 7, opNOP},
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0xA0: opcode{"LDY", 2, 2, modeImmediate, regY, opLDR},
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0xA0: opcode{"LDY", 2, 2, buildOpLoad(modeImmediate, regY)},
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0xA1: opcode{"LDX", 2, 6, modeIndexedIndirectX, regA, opLDR},
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0xA1: opcode{"LDX", 2, 6, buildOpLoad(modeIndexedIndirectX, regA)},
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0xA2: opcode{"LDX", 2, 2, modeImmediate, regX, opLDR},
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0xA4: opcode{"LDY", 2, 3, modeZeroPage, regY, opLDR},
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0xA5: opcode{"LDA", 2, 3, modeZeroPage, regA, opLDR},
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0xA6: opcode{"LDX", 2, 3, modeZeroPage, regX, opLDR},
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0xA9: opcode{"LDA", 2, 2, modeImmediate, regA, opLDR},
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0xA2: opcode{"LDX", 2, 2, buildOpLoad(modeImmediate, regX)},
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0xA4: opcode{"LDY", 2, 3, buildOpLoad(modeZeroPage, regY)},
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0xA5: opcode{"LDA", 2, 3, buildOpLoad(modeZeroPage, regA)},
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0xA6: opcode{"LDX", 2, 3, buildOpLoad(modeZeroPage, regX)},
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0xA9: opcode{"LDA", 2, 2, buildOpLoad(modeImmediate, regA)},
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0xAC: opcode{"LDY", 3, 4, modeAbsolute, regY, opLDR},
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0xAD: opcode{"LDA", 3, 4, modeAbsolute, regA, opLDR},
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0xAE: opcode{"LDX", 3, 4, modeAbsolute, regX, opLDR},
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0xAA: opcode{"TAX", 1, 2, buildOPTransfer(regA, regX)},
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0xA8: opcode{"TAY", 1, 2, buildOPTransfer(regA, regY)},
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0xBA: opcode{"TSX", 1, 2, buildOPTransfer(regSP, regX)},
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0x8A: opcode{"TXA", 1, 2, buildOPTransfer(regX, regA)},
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0x9A: opcode{"TXS", 1, 2, buildOPTransfer(regX, regSP)},
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0x98: opcode{"TYA", 1, 2, buildOPTransfer(regY, regA)},
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0xB1: opcode{"LDX", 2, 5, modeIndirectIndexedY, regA, opLDR}, // Extra cycles
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0xAC: opcode{"LDY", 3, 4, buildOpLoad(modeAbsolute, regY)},
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0xAD: opcode{"LDA", 3, 4, buildOpLoad(modeAbsolute, regA)},
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0xAE: opcode{"LDX", 3, 4, buildOpLoad(modeAbsolute, regX)},
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0xB4: opcode{"LDY", 2, 4, modeZeroPageX, regY, opLDR},
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0xB5: opcode{"LDA", 2, 4, modeZeroPageX, regA, opLDR},
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0xB6: opcode{"LDX", 2, 4, modeZeroPageY, regX, opLDR},
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0xB1: opcode{"LDX", 2, 5, buildOpLoad(modeIndirectIndexedY, regA)}, // Extra cycles
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0xB9: opcode{"LDA", 3, 4, modeAbsoluteY, regA, opLDR}, // Extra cycles
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0xBC: opcode{"LDY", 3, 4, modeAbsoluteX, regY, opLDR}, // Extra cycles
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0xBD: opcode{"LDA", 3, 4, modeAbsoluteX, regA, opLDR}, // Extra cycles
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0xBE: opcode{"LDX", 3, 4, modeAbsoluteY, regX, opLDR}, // Extra cycles
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0xB4: opcode{"LDY", 2, 4, buildOpLoad(modeZeroPageX, regY)},
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0xB5: opcode{"LDA", 2, 4, buildOpLoad(modeZeroPageX, regA)},
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0xB6: opcode{"LDX", 2, 4, buildOpLoad(modeZeroPageY, regX)},
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0xB9: opcode{"LDA", 3, 4, buildOpLoad(modeAbsoluteY, regA)}, // Extra cycles
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0xBC: opcode{"LDY", 3, 4, buildOpLoad(modeAbsoluteX, regY)}, // Extra cycles
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0xBD: opcode{"LDA", 3, 4, buildOpLoad(modeAbsoluteX, regA)}, // Extra cycles
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0xBE: opcode{"LDX", 3, 4, buildOpLoad(modeAbsoluteY, regX)}, // Extra cycles
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}
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func executeLine(s *state, line []uint8) {
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@ -4,7 +4,7 @@ import (
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"testing"
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)
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func TestLDA(t *testing.T) {
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func TestLoad(t *testing.T) {
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var s state
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executeLine(&s, []uint8{0xA9, 0x42})
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@ -66,4 +66,51 @@ func TestLDA(t *testing.T) {
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t.Error("Error in LDA (oper,X)")
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}
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s.memory[0x86] = 0x28
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s.memory[0x87] = 0x40
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s.registers.setY(0x10)
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s.memory[0x4038] = 0x99
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executeLine(&s, []uint8{0xB1, 0x86})
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if s.registers.getA() != 0x99 {
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t.Error("Error in LDA (oper),Y")
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}
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}
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func TestTransfer(t *testing.T) {
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var s state
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s.registers.setA(0xB0)
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executeLine(&s, []uint8{0xAA})
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if s.registers.getX() != 0xB0 {
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t.Error("Error in TAX")
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}
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s.registers.setA(0xB1)
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executeLine(&s, []uint8{0xA8})
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if s.registers.getY() != 0xB1 {
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t.Error("Error in TAY")
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}
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s.registers.setSP(0xB2)
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executeLine(&s, []uint8{0xBA})
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if s.registers.getX() != 0xB2 {
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t.Error("Error in TSX")
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}
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s.registers.setX(0xB3)
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executeLine(&s, []uint8{0x8A})
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if s.registers.getA() != 0xB3 {
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t.Error("Error in TXA")
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}
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s.registers.setX(0xB4)
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executeLine(&s, []uint8{0x9A})
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if s.registers.getSP() != 0xB4 {
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t.Error("Error in TXS")
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}
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s.registers.setY(0xB5)
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executeLine(&s, []uint8{0x98})
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if s.registers.getA() != 0xB5 {
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t.Error("Error in TYA")
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}
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}
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33
registers.go
33
registers.go
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@ -1,13 +1,12 @@
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package main
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const (
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regA = 0
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regX = 1
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regY = 2
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regP = 4
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regS = 5
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regPC = 6 // 2 bytes
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regNone = 10
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regA = 0
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regX = 1
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regY = 2
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regP = 4
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regSP = 5
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regPC = 6 // 2 bytes
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)
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type registers struct {
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@ -16,20 +15,20 @@ type registers struct {
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func (r *registers) getRegister(i int) uint8 { return r.data[i] }
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func (r *registers) getA() uint8 { return r.data[regA] }
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func (r *registers) getX() uint8 { return r.data[regX] }
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func (r *registers) getY() uint8 { return r.data[regY] }
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func (r *registers) getP() uint8 { return r.data[regP] }
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func (r *registers) getS() uint8 { return r.data[regS] }
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func (r *registers) getA() uint8 { return r.data[regA] }
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func (r *registers) getX() uint8 { return r.data[regX] }
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func (r *registers) getY() uint8 { return r.data[regY] }
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func (r *registers) getP() uint8 { return r.data[regP] }
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func (r *registers) getSP() uint8 { return r.data[regSP] }
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func (r *registers) setRegister(i int, v uint8) {
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r.data[i] = v
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}
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func (r *registers) setA(v uint8) { r.setRegister(regA, v) }
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func (r *registers) setX(v uint8) { r.setRegister(regX, v) }
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func (r *registers) setY(v uint8) { r.setRegister(regY, v) }
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func (r *registers) setP(v uint8) { r.setRegister(regP, v) }
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func (r *registers) setS(v uint8) { r.setRegister(regS, v) }
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func (r *registers) setA(v uint8) { r.setRegister(regA, v) }
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func (r *registers) setX(v uint8) { r.setRegister(regX, v) }
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func (r *registers) setY(v uint8) { r.setRegister(regY, v) }
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func (r *registers) setP(v uint8) { r.setRegister(regP, v) }
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func (r *registers) setSP(v uint8) { r.setRegister(regSP, v) }
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func (r *registers) getPC() uint16 {
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return uint16(r.data[regPC])*256 + uint16(r.data[regPC+1])
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