diff --git a/.gitignore b/.gitignore index d5d60b9..3fe208a 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,5 @@ .vscode SDL2.dll -a2sdl.exe \ No newline at end of file +a2sdl.exe +frontend/a2sdl/a2sdl +frontend/a2fyne/a2fyne \ No newline at end of file diff --git a/core6502/nmos6502_test.go b/core6502/nmos6502_test.go index 5992004..dfad1c3 100644 --- a/core6502/nmos6502_test.go +++ b/core6502/nmos6502_test.go @@ -17,7 +17,7 @@ func TestNMOS6502(t *testing.T) { func executeSuite(t *testing.T, s *State, stepAddress uint16, steps uint8, showStep bool, traceCPUStep uint8) { s.reg.setPC(0x0400) currentStep := uint8(255) - for true { + for { testCase := s.mem.Peek(stepAddress) if testCase != currentStep { currentStep = testCase diff --git a/core6502/registers_test.go b/core6502/registers_test.go index 403c1d7..0625c42 100644 --- a/core6502/registers_test.go +++ b/core6502/registers_test.go @@ -4,8 +4,7 @@ import "testing" func TestRegA(t *testing.T) { var r registers - var data uint8 - data = 200 + data := uint8(200) r.setA(data) if r.getA() != data { t.Error("Error storing and loading A") @@ -13,8 +12,7 @@ func TestRegA(t *testing.T) { } func TestRegPC(t *testing.T) { var r registers - var data uint16 - data = 0xc600 + data := uint16(0xc600) r.setPC(data) if r.getPC() != data { t.Error("Error storing and loading PC") diff --git a/go.mod b/go.mod index 61885f2..b9364e4 100644 --- a/go.mod +++ b/go.mod @@ -15,6 +15,5 @@ require ( golang.org/x/sys v0.0.0-20201014080544-cc95f250f6bc // indirect golang.org/x/tools v0.0.0-20201013201025-64a9e34f3752 // indirect gopkg.in/check.v1 v1.0.0-20200902074654-038fdea0a05b // indirect - gopkg.in/yaml.v2 v2.3.0 // indirect gopkg.in/yaml.v3 v3.0.0-20200615113413-eeeca48fe776 // indirect ) diff --git a/traceApplecorn.go b/traceApplecorn.go index 5fdf4b8..cec4f90 100644 --- a/traceApplecorn.go +++ b/traceApplecorn.go @@ -132,7 +132,6 @@ func (t *traceApplecorn) inspect() { s = "OSNRDCH()" skip = t.skipConsole case 0xffce: - s = "OSFIND(?)" if regA == 0 { s = fmt.Sprintf("OSFIND('close',HANDLE=%v", regY) } else {